Abstract: A NAND flash memory device having memory cells for storing data includes a fuse circuit configured to store option information for operation of the NAND flash memory device as logic codes. A register circuit includes registers for temporarily storing the logic codes stored in the fuse circuit. A test circuit is configured to change the logic code stored in the register circuit and store the changed logic code irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device. A processor is configured to control operation of the NAND flash memory device.

Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Abstract: A method of testing a non-volatile memory device on a wafer is disclosed. The method includes performing an erase operation and a first verify operation about every memory cell in the non-volatile memory device, storing data of a first latch in a page buffer for storing result in accordance with the first verify operation in a second latch, and setting the data of the first latch to data indicating pass of the verifying, and performing a soft program and a second verify operation about every memory cell.

Abstract: A method of operating a flash memory device includes reading a first bit data by employing a first read voltage or a second read voltage higher than the first read voltage according to a program state of a first flag cell. The first flag cell is programmed when the first bit data is programmed into the MLC. A second bit data may be read by employing a third read voltage that is higher than the first read voltage or the second read voltage, or by employing the first read voltage and the third read voltage according to a program state of a second flag cell. The second flag cell is programmed when the second bit data is programmed into the MLC. Alternatively to reading the second bit data, the second bit data is fixed to a set data and the set data is output.

Abstract: A method includes performing test bit setting; programming a first page using data set by the test bit setting, and storing a fail status bit in a page buffer, which is connected to a first bit line having a fail status, based on a verification result of the test program; performing a test program and verification on a second page based on a test program and fail status bit storage result of a preceding page, and storing a fail status bit in the page buffer, which is connected to a second bit line having a fail status, based on a verification result of the test program and verification; and after a test program, verification, and fail status bit setting with respect to the entire pages of a memory block are completed, outputting data of the page buffer.

Abstract: A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected in series; performing soft programming operation by applying a soft programming voltage to word lines of the selected memory cell block; and programming the side memory cells by applying a programming voltage to the side memory cells.

Abstract: A pump circuit includes a plurality of transfer elements, capacitors, and controllers. The transfer elements are connected in series between a power supply terminal and an output terminal. The capacitors charge two terminals of each of the transfer elements according to first and second clock signals, respectively. Each of the controllers includes first and second switch elements, which are operated in opposite manners in response to the first or second clock signal to control each of the transfer elements.

Abstract: In a programming method of a non-volatile memory device, a program operation is performed by applying a program voltage to a selected word line and a first pass voltage to unselected word lines. The first pass voltage shifts to a second pass voltage having a level lower than that of the first pass voltage. A verify operation is performed by applying a verify voltage to the selected word line. The verify voltage has a level lower than that of the second pass voltage.

Abstract: A non-volatile memory device comprises an even bit line and an odd bit line contacting to a memory cell array. A register unit includes a first register and a second register for temporarily storing data. A detecting node detects a voltage level of the specific bit line or the specific register which is connected to the bit lines and the registers. A selecting unit of the bit line includes a first variable voltage input terminal and a second variable voltage input terminal. The first variable voltage input terminal applies a first variable voltage of a specific voltage level to the even bit line in response to an even discharge signal. The second variable voltage input terminal applies a second variable voltage of a specific voltage level to the odd bit line in response to an odd discharge signal.

Abstract: A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.

Abstract: In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node.

Abstract: A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.

Abstract: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.

Abstract: A voltage conversion circuit includes a reference voltage generation unit for generating a reference voltage having a uniform level regardless of a level of an input voltage varying according to an operation mode; and a driver unit for generating and outputting an active voltage or a standby voltage using the reference voltage output by the reference voltage generation unit according to a control signal.

Abstract: A NAND flash memory device having memory cells for storing data includes a fuse circuit configured to store option information for operation of the NAND flash memory device as logic codes. A register circuit includes registers for temporarily storing the logic codes stored in the fuse circuit. A test circuit is configured to change the logic code stored in the register circuit and store the changed logic code irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device. A processor is configured to control operation of the NAND flash memory device.

Abstract: A non-volatile memory device comprises an even bit line and an odd bit line contacting to a memory cell array. A register unit includes a first register and a second register for temporarily storing data. A detecting node detects a voltage level of the specific bit line or the specific register which is connected to the bit lines and the registers. A selecting unit of the bit line includes a first power input terminal and a second power input terminal. The first power input terminal applies a first power of a specific voltage level to the even bit line in response to an even discharge signal. The second power input terminal applies a second power of a specific voltage level to the odd bit line in response to an odd discharge signal.

Abstract: A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell.

Abstract: Disclosed herein is a continuously operable seat-reclining device having an improved actuator to substantially carry out a reclining operation of the reclining device such that an actuating force of a shaft is uniformly transmitted to the entirety of a coupling. The continuously operable seat-reclining device basically comprises an upper teeth bracket and a lower teeth bracket securely fixed to a seat back frame and a cushion frame, respectively, the upper teeth bracket being provided with upper teeth, the lower teeth bracket being provided with lower teeth, the upper teeth of the upper teeth bracket being engaged with the lower teeth of the lower teeth bracket, a cam hole formed at the center of the lower teeth bracket, and an actuator disposed between the cam hole and the cam-maintaining ring for moving the upper teeth bracket relative to the lower teeth bracket.

Abstract: A reclining device of a vehicle seat for easily locking and releasing the vehicle seat so as to increase performance of the vehicle seat and to improve quality thereof. The reclining device is easily assembled, by removing minor shortcomings that may occur during the assembly process, and enhances engagement of the locking teeth with the upper teeth when the reclining device is installed to a vehicle, so that the convenience as well as quality, strength, and durability of the reclining device are enhanced.

Abstract: A reclining device of a vehicle seat for easily locking and releasing the vehicle seat so as to increase performance of the vehicle seat and to improve quality thereof. The reclining device is easily assembled, by removing minor shortcomings that may occur during the assembly process, and enhances engagement of the locking teeth with the upper teeth when the reclining device is installed to a vehicle, so that the convenience as well as quality, strength, and durability of the reclining device are enhanced.