Abstract: Embodiments disclose a level shifter including a logic unit configured to receive timing data and channel data and output an edge signal and a channel signal at a time point defined in the timing data, and a channel selection unit configured to select at least one channel from among a plurality of connected channels according to the channel signal and transmit the edge signal, and a display device including the same.

Abstract: The present disclosure relates to a clock generator and a display device including the same. The clock generator includes a first clock generation circuit configured to output a clock, data, and a timing control signal; a first wiring through which the clock is serially transmitted; a second wiring through which the data is serially transmitted; a third wiring through which a pulse of the timing control signal is serially transmitted; a second clock generation circuit connected to the first clock generation circuit through the first wiring, the second wiring, and the third wiring and configured to generate pre-clocks in which phases are sequentially shifted based on the data and the clock; and a clock adjustment circuit configured to receive the pulse of the timing control signal and the pre-clock and output an output clock.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: Disclosed herein are a display device capable of reducing the number of transmission lines by enabling a master circuit to perform communication with a plurality of slave circuits, which utilize different interfaces, through a common transmission line in a time divisional manner, and an interface method thereof. A timing controller uses a common transmission line of a gamma voltage generator and a level shifter which respectively utilize first and second interfaces and perform communication using the first and second interfaces in a time divisional manner.

Abstract: A chip on film and a display device including the same selectively outputs gate transmission signals and data outputs to reduce the number of output pads in a data driving IC. The COF includes first to third groups of data input pads, gate input pads, and output pads. A data driving IC includes first to third groups of output buffers, a first switchable output unit configured to selectively supply gate transmission signals and an output of the first group of output buffers to the first group of output pads, and a second switchable output unit configured to selectively supply the gate transmission signals and an output of the third group of output buffers to the third group of output pads. An output of the second group of output buffers is supplied to the second group of output pads between the first and the third groups of output pads.

Abstract: A memory module includes: a plurality of first memory ranks that belong to a first group; a plurality of second memory ranks that belong to a second group; and a rank mapping circuit suitable for mapping a defective first memory rank among the first memory ranks to a defect-free second memory rank among the second memory ranks.

Abstract: A chip on film and a display device including the same selectively outputs gate transmission signals and data outputs to reduce the number of output pads in a data driving IC. The COF includes first to third groups of data input pads, gate input pads, and output pads. A data driving IC includes first to third groups of output buffers, a first switchable output unit configured to selectively supply gate transmission signals and an output of the first group of output buffers to the first group of output pads, and a second switchable output unit configured to selectively supply the gate transmission signals and an output of the third group of output buffers to the third group of output pads. An output of the second group of output buffers is supplied to the second group of output pads between the first and the third groups of output pads.

Abstract: Disclosed herein are a display device capable of reducing the number of transmission lines by enabling a master circuit to perform communication with a plurality of slave circuits, which utilize different interfaces, through a common transmission line in a time divisional manner, and an interface method thereof. A timing controller uses a common transmission line of a gamma voltage generator and a level shifter which respectively utilize first and second interfaces and perform communication using the first and second interfaces in a time divisional manner.

Abstract: A memory module includes: a plurality of first memory ranks that belong to a first group; a plurality of second memory ranks that belong to a second group; and a rank mapping circuit suitable for mapping a defective first memory rank among the first memory ranks to a defect-free second memory rank among the second memory ranks.

Abstract: A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.

Abstract: A method for processing a touch signal in a mobile terminal and a mobile terminal using the same are disclosed, wherein the method comprises: detecting a shaking of a mobile terminal by using a mobile terminal shaking detection sensor within a predetermined time from a touched time while a touch screen is being touched; and outputting an output signal based on the detected shaking.

Abstract: Disclosed is checking a drive state of a backlight lamp of a liquid crystal display device and notifying to an external entity whether it is normally driven in which level or is difficult to be normally driven.

Abstract: The present invention relates to a lightning protection apparatus using a TN-C common ground. A lightning protection apparatus using a TN-C common ground according to the present invention, which is disposed between a power source part and load facilities and is connected in series thereto in order to protect the power source part and the load facilities from lightning, includes: an input part surge protection circuit connecting to the power source part; an output part surge protection circuit connecting to the load facilities; a double winding transformer having a primary part and a secondary part, which connect to the input part surge protection circuit and the output part surge protection circuit, respectively; and common ground members connecting, respectively, to the input part surge protection circuit, the double winding transformer, the output part surge protection circuit, and the load facilities such that electric potentials applied to all of the former are the same as a reference electric potential.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: A semiconductor device that allows an image sensor (in an upper area of a SiP semiconductor device) to exchange signals with a device in a lower area of a SiP semiconductor device. A semiconductor device includes at least one of: A semiconductor substrate having a photodiode area and a transistor area. A PMD (Pre Metal Dielectric) layer formed on and/or over the semiconductor substrate. At least one metal layers formed on and/or over the PMD layer. A first penetrating electrode penetrating the PMD layer and the at least one metal layers. A second penetrating electrode penetrating the semiconductor substrate and connected to the first penetrating electrode.

Abstract: A method for processing a touch signal in a mobile terminal and a mobile terminal using the same are disclosed, wherein the method comprises: detecting a shaking of a mobile terminal by using a mobile terminal shaking detection sensor within a predetermined time from a touched time while a touch screen is being touched; and outputting an output signal based on the detected shaking.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a conducting layer, a first insulating film formed on the semiconductor substrate and having a via hole formed therein, a lower barrier film formed on an inside wall of the via hole, a first metal wiring formed on the lower barrier film, a second insulating film formed on the first metal wiring and the first insulating film, the second insulating film being provided with a trench which has a width greater than a width of the via hole, an upper barrier film formed on a lower surface of the trench, a second metal wiring formed on the upper barrier film, and a sidewall barrier film formed on sidewalls of the upper barrier film and the second metal wiring. The sidewall barrier film has an L-shaped mirror-symmetrical structure.