Abstract: An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and light loss may be reduced.

Abstract: A method of effectively fabricating a semiconductor device involves separately fabricating a first substrate having a transistor layer and a second substrate having a metal wire layer, and stacking the first and second substrates. A transistor on the first substrate is electrically connected to a metal wire on the second substrate through a connection electrode.

Abstract: A semiconductor device according to embodiments may include an interposer, a plurality of devices stacked on the interposer, a cooling device provided in at least one of the devices and including a passage for a cooling material, and a connection electrode provided between the devices, in which the connection electrode connects a signal electrode in an upper device to a signal electrode in a lower device.

Abstract: A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.

Abstract: For a semiconductor device having copper wiring, an exemplary method according to an embodiment of the present invention may include forming a first insulation layer on a silicon substrate having a transistor thereon; forming a contact hole by etching the first insulation layer; forming a metal plug so as to fill the contact hole; forming a second insulation layer on the metal plug; forming a trench exposing an upper surface of the metal plug by partially removing the second insulation layer; sputter-etching an interior wall and bottom surface of the trench with a plasma; and forming a copper line layer so as to fill the sputter-etched trench. According to this method, electrical contact between a metal plug and a copper line layer may be maintained or improved prevented by reducing or removing by-products on the metal plug using the sputter-etching process.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: Embodiments relate to a CMOS image sensor and a manufacturing a CMOS image sensor, that may be capable of enhancing a focusing function of light by forming a reflective layer between a micro lens and a photodiode, and may improve a sensitivity of an image sensor.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a conducting layer, a first insulating film formed on the semiconductor substrate and having a via hole formed therein, a lower barrier film formed on an inside wall of the via hole, a first metal wiring formed on the lower barrier film, a second insulating film formed on the first metal wiring and the first insulating film, the second insulating film being provided with a trench which has a width greater than a width of the via hole, an upper barrier film formed on a lower surface of the trench, a second metal wiring formed on the upper barrier film, and a sidewall barrier film formed on sidewalls of the upper barrier film and the second metal wiring. The sidewall barrier film has an L-shaped mirror-symmetrical structure.

Abstract: A method for forming metal lines in a semiconductor device includes forming a first insulating film having a via hole over a semiconductor substrate with a conductive layer, forming a via metal line for filling the via hole, forming, over the first insulating film, a second insulating film having a trench, the trench having a larger width than that of the via hole, and forming a trench metal line for filling the trench. The second insulating film is made of a low-K material including SiOC, and the first insulating film is made of a different material from the second insulating film.

Abstract: The present invention is directed to a method of manufacturing silicide used to reduce a contact resistance at a contact of a semiconductor device and a semiconductor device with the silicide manufactured by the same method. The method comprises the steps of: (a) cleaning a semiconductor substrate with a transistor formed thereon, the transistor including a source electrode, a drain electrode and a gate electrode; (b) placing the cleaned semiconductor substrate into a sputter chamber in a deposition equipment, and forming silicide at the same time of depositing a metal film under a state where the semiconductor substrate is heated at a temperature of 450-600° C.; (c) removing residual metal film not used for the formation of silicide; and (d) annealing the semiconductor substrate.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide device above the deposition stop time detection pattern; depositing copper on the substrate; and stopping deposition of the copper by an electric signal being generated when the two detection electrodes are electrically connected by the copper deposited in the two trench structure.

Abstract: A method of manufacturing a semiconductor device. A cobalt film is formed on a wafer including gate, source, and drain regions. An initial protection metal film is formed with an initial amount of a protection metal film material on the cobalt film. The wafer is thermally treated to form a cobalt silicide film. An additional protection metal film is formed with an additional amount of the protection metal film material.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide device above the deposition stop time detection pattern; depositing copper on the substrate; and stopping deposition of the copper by an electric signal being generated when the two detection electrodes are electrically connected by the copper deposited in the two trench structure.

Abstract: A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and second areas, respectively, and measuring a resistance of the standard pattern. The method also includes forming a misalignment inspection pattern consisting of a first area and a second area on a predetermined area within a semiconductor substrate, implanting first and second conduction type impurity ions into the misalignment inspection pattern and active regions on the semiconductor substrate, respectively, and measuring a resistance of the misalignment inspection pattern. The method concludes by comparing the resistance of the standard pattern with the resistance of the misalignment inspection pattern.

Abstract: For a semiconductor device having copper wiring, an exemplary method according to an embodiment of the present invention may include forming a first insulation layer on a silicon substrate having a transistor thereon; forming a contact hole by etching the first insulation layer; forming a metal plug so as to fill the contact hole; forming a second insulation layer on the metal plug; forming a trench exposing an upper surface of the metal plug by partially removing the second insulation layer; sputter-etching an interior wall and bottom surface of the trench with a plasma; and forming a copper line layer so as to fill the sputter-etched trench. According to this method, electrical contact between a metal plug and a copper line layer may be maintained or improved prevented by reducing or removing by-products on the metal plug using the sputter-etching process.

Abstract: A “black belt” phenomenon that may be caused by an eddy of a slurry may be prevented when a wafer is polished by a chemical mechanical polishing (CMP) apparatus that includes a polishing pad to be supplied with the slurry, a polishing head including a top ring adapted to hold a wafer, and a buffer ring forming a buffer space between an edge region of the wafer and an eddy region of the slurry that may be formed in front of the polishing head.

Abstract: A formation method of metal wiring of a semiconductor device is disclosed. According to one example, an example method may include forming a metal wire on a pre metal dielectric (“PMD”) on a semiconductor substrate; patterning and sintering the metal wire; forming an insulating layer on the metal wire and the PMD; and forming a via hole in the insulating layer. The example method may further include forming a barrier metal layer made of multiple metal layers on inner wall of the via hole and upper surface of the insulating layer using physical vapor deposition and chemical vapor deposition; filling up inside the via hole by forming a metallic material on the metal layer; and forming a metallic material via by chemical mechanical polishing of the metallic material and the barrier metal layer until the insulating layer is exposed.

Abstract: A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing a metal layer on a substrate having a predetermined structure; patterning a bottom metal layer through etching the metal layer; forming a pad electrically connecting the bottom metal layer to a scribe area; forming an insulating layer on the substrate including the bottom metal layer; forming a via hole and a trench, in which an upper metal layer is formed, on the insulating layer, the via hole connecting the bottom metal layer with the upper metal layer; forming a plating layer by means of electroplating; and performing a planarization process for the plating layer. Accordingly, the present invention needs not a separate seed layer because the bottom metal layer is used as a seed layer.