Patents by Inventor Jae Yoo

Jae Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12350026
    Abstract: A photoplethysmography sensor that includes a photoelectric conversion element including a first terminal and a second terminal, and that receives light reflected from a blood vessel and generates a current corresponding to the received light, a current-to-voltage converter that receives the generated current through a first input terminal and a second input terminal, and generates an output voltage corresponding to the received current, and a switch that, in response to a control signal of a first level, connects the first and second terminals of the photoelectric conversion element respectively to the first and second input terminals of the current-to-voltage converter and in response to the control signal of a second level different from the first level, connects the first and second terminals of the photoelectric conversion element respectively to the second and first input terminals of the current-to-voltage converter.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: July 8, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Jin Jung, Long Yan, Seoung Jae Yoo, Yun-Cheol Han
  • Publication number: 20250187435
    Abstract: A method of providing distance-to-empty information of a vehicle includes determining, by a controller, based on an initial distance to empty (DTE), which is a distance to empty at the beginning of vehicle driving, an initial predicted DTE, which is a predicted distance to empty that changes as the vehicle is driven, determining, by the controller, a current DTE, which is an actual distance to empty, in real time for each set distance during vehicle driving, and controlling, by the controller, the operation of the display device to display actual DTE history information representing a history of change in the determined current DTE as an actual driving distance increases during vehicle driving along with the initial predicted DTE information, and an information provision apparatus configured to perform the method.
    Type: Application
    Filed: August 6, 2024
    Publication date: June 12, 2025
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Kyeong Soo Song, Yong Kak Choi, Jae Yun Shim, Jin Hyung Lee, Seung Jae Yoo, Young Rang Lee, Jong Chan Jun, Hye Joo Lee, Hyun Jong Ha, Jae Yeong Jeong, Gum Jin Park, Sung Chan Park
  • Publication number: 20250177956
    Abstract: The present disclosure discloses a catalyst for hydrogenolysis reaction of waste plastics, a method for producing the same, and a method for converting the waste plastics using the same. The catalyst comprises a ceria carrier; and a transition metal supported on the carrier. The catalyst has the effect of producing hydrocarbon compounds such as naphthas, fuels, and lubricants from waste plastics at a low temperature of 200 to 250° C.
    Type: Application
    Filed: November 21, 2024
    Publication date: June 5, 2025
    Inventors: Chun-Jae YOO, Kwang Ho KIM, Chang Soo KIM, Kyeongsu KIM, Jae Wook CHOI, Dong Jin SUH, Jeong-Myeong HA, Young Hyun YOON, Hyun Joo LEE, Achmad Buhori
  • Publication number: 20250167691
    Abstract: Disclosed is a lagging leg removal phase shift full bridge converter circuit. The circuit may include: a primary circuit including Leg 1, Leg 2, Leg 3, and Leg 4, applying a switching control signal to a switch included in each leg, and switching the switching control signal to output a first AC voltage; a secondary circuit including a plurality of modules which transforms the first AC voltage into a second AC voltage according to a predetermined transform ratio, and performs rectification and filtering for the second AC voltage; and a controller generating the switching control signal, and supplying the generated switching control signal to the switch included in each leg.
    Type: Application
    Filed: November 25, 2022
    Publication date: May 22, 2025
    Inventors: Je Hyun YI, Hyun Jae YOO, Jeong Jun SEO
  • Patent number: 12266568
    Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Hui Jae Yoo, Tejaswi K. Indukuri, Ramanan V. Chebiam, James S. Clarke
  • Patent number: 12262477
    Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 25, 2025
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Do Jae Yoo, Yong Gil Namgung, Jong Hoon Shin, Sang Soon Choi, Young Chul An
  • Patent number: 12255137
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Grant
    Filed: January 22, 2024
    Date of Patent: March 18, 2025
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Rishabh Mehandru
  • Patent number: 12249571
    Abstract: According to an aspect of the present disclosure, there is provided a pre-mold substrate including an electroconductive base member, which includes a first pre-mold groove formed in a bottom surface and a second pre-mold groove formed in a top surface and constitutes a circuit pattern; a first pre-mold resin disposed in the first pre-mold groove; and a second pre-mold resin disposed in the second pre-mold groove.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 11, 2025
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Kwang Jae Yoo, Jong Hoe Ku, In Seob Bae
  • Publication number: 20250050783
    Abstract: An apparatus provides information on a distance to empty (DTE) of a vehicle and an information providing method is performed thereby. The apparatus includes a display device configured to display DTE information of a vehicle and a controller configured to control operation of the display device. The controller determines low fuel efficiency-related information and high fuel efficiency-related information based on a current vehicle driving condition. The controller determines a low DTE value and a high DTE value based on the low fuel efficiency-related information, the high fuel efficiency-related information, and a current available battery energy. The controller also determines a current DTE value indicating a real-time DTE and controls operation of the display device to display the low DTE value, the high DTE value, and the current DTE value.
    Type: Application
    Filed: January 16, 2024
    Publication date: February 13, 2025
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Kyeong Soo Song, Jin Hyung Lee, Seung Jae Yoo, Hyun Jong Ha, Jae Yeong Jeong, Eun Bin Kim, Seon Min Kim, Jong Hoon Ahn
  • Patent number: 12224202
    Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Ehren Mannebach, Patrick Morrow, Anh Phan, Willy Rachmady, Hui Jae Yoo
  • Patent number: 12187317
    Abstract: An advanced driver assistance system is provided. The advanced driver assistance system of the vehicle comprises a communicator configured to communicate with an obstacle detector configured to detect an obstacle; and a processor configured to determine a riding intention of a user in response to reception of a door unlocking instruction, obtain location information of other vehicles based on obstacle information detected by the obstacle detector in response to determining that the riding intention exists, determine a collision possibility with other vehicles based on the location information of other vehicles, and control output of notification information for a collision in response to determining that the collision possibility exists.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: January 7, 2025
    Assignees: Hyundai Motor Company, Kia Corporation
    Inventor: Jeong-Jae Yoo
  • Publication number: 20250004422
    Abstract: Proposed are an apparatus for recording a holographic interference pattern and a method of recording a holographic interference pattern using the apparatus, the apparatus and the method being capable of simplifying a process of aligning a light source and a photosensitive material in order to record a holographic interference pattern on a three-dimensional coordinate system and then realigning the light source and the photosensitive material in order to record a different holographic interference pattern.
    Type: Application
    Filed: May 30, 2022
    Publication date: January 2, 2025
    Applicant: LG Chem, Ltd.
    Inventors: Min Soo Song, Sung Yeon Kim, Yeon Jae Yoo, Joon Young Lee
  • Patent number: 12175727
    Abstract: Disclosed is an automatic image classification and processing method based on the continuous processing structure of multiple artificial intelligence models. An automatic image classification and processing method based on a continuous processing structure of multiple artificial intelligence models includes receiving image data, generating a first feature extraction value by inputting the image data into a first feature extraction model among feature extraction models, generating a second feature extraction value by inputting the image data into a second feature extraction model among the feature extraction models, and determining a classification value of the image data by inputting the first and second feature extraction values into a classification model.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: December 24, 2024
    Assignee: CROWDWORKS, INC.
    Inventors: Min Woo Park, Sang Jae Yoo, Tae Sang Park
  • Publication number: 20240391384
    Abstract: An intersection right turn hazard warning method using an intersection entry guidance system of a subject vehicle reduces a collision hazard that may occur upon a right turn of the subject vehicle at an intersection. The method may include determining intersection information and vehicle right turn information from a vehicle information sensor, traffic light-blinking pattern information of left/right crosswalk traffic lights and a road-traveling traffic light from a first vehicle exterior information sensor. The method may also include determining longitudinal movement pattern information of an object at the intersection from a second vehicle exterior information sensor. The method May further include outputting an intersection scenario-specific warning to a human machine interface (HMI) and/or a surround view monitor (SVM) upon a right turn of the subject vehicle at the intersection according to an intersection scenario selected from a intersection situation classification table.
    Type: Application
    Filed: November 7, 2023
    Publication date: November 28, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventor: Jeong-Jae Yoo
  • Patent number: 12150297
    Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Arnab Sen Gupta, Matthew V. Metz, Elliot N. Tan, Hui Jae Yoo, Travis W. Lajoie, Van H. Le, Pei-Hua Wang
  • Patent number: 12148734
    Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot Tan, Hui Jae Yoo, Noriyuki Sato, Travis W. Lajoie, Van H. Le, Thoe Michaelos
  • Patent number: 12148806
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Publication number: 20240379905
    Abstract: A light emitting diode according to an exemplary embodiment of the present disclosure includes a first conductivity type semiconductor layer; an active region including a barrier layer and a well layer; a strain control layer disposed between the first conductivity type semiconductor layer and the active region; a superlattice layer disposed between the strain control layer and the active region; a second conductivity type semiconductor layer disposed on the active region; and an electron blocking layer disposed between the active region and the second conductivity type semiconductor layer, in which the first conductivity type semiconductor layer and the well layer are represented by a predetermined formula, and a ratio of a mole fraction of In to a mole fraction of Ga in the first conductivity type semiconductor layer and a ratio of a mole fraction of In to a mole fraction of Ga in the well layer satisfy a predetermined equation.
    Type: Application
    Filed: May 6, 2024
    Publication date: November 14, 2024
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventor: Hong Jae YOO
  • Publication number: 20240371700
    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Intel Corporation
    Inventors: Aaron D. LILAK, Ehren MANNEBACH, Anh PHAN, Richard E. SCHENKER, Stephanie A. BOJARSKI, Willy RACHMADY, Patrick R. MORROW, Jeffrey D. BIELEFELD, Gilbert DEWEY, Hui Jae YOO
  • Publication number: 20240365475
    Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Do Jae YOO, Yong Gil NAMGUNG, Jong Hoon SHIN, Sang Soon CHOI, Young Chul AN