Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Abstract: According to an aspect of the present disclosure, there is provided a pre-mold substrate including an electroconductive base member, which includes a first pre-mold groove formed in a bottom surface and a second pre-mold groove formed in a top surface and constitutes a circuit pattern; a first pre-mold resin disposed in the first pre-mold groove; and a second pre-mold resin disposed in the second pre-mold groove.

Abstract: An apparatus provides information on a distance to empty (DTE) of a vehicle and an information providing method is performed thereby. The apparatus includes a display device configured to display DTE information of a vehicle and a controller configured to control operation of the display device. The controller determines low fuel efficiency-related information and high fuel efficiency-related information based on a current vehicle driving condition. The controller determines a low DTE value and a high DTE value based on the low fuel efficiency-related information, the high fuel efficiency-related information, and a current available battery energy. The controller also determines a current DTE value indicating a real-time DTE and controls operation of the display device to display the low DTE value, the high DTE value, and the current DTE value.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

Abstract: An advanced driver assistance system is provided. The advanced driver assistance system of the vehicle comprises a communicator configured to communicate with an obstacle detector configured to detect an obstacle; and a processor configured to determine a riding intention of a user in response to reception of a door unlocking instruction, obtain location information of other vehicles based on obstacle information detected by the obstacle detector in response to determining that the riding intention exists, determine a collision possibility with other vehicles based on the location information of other vehicles, and control output of notification information for a collision in response to determining that the collision possibility exists.

Abstract: Proposed are an apparatus for recording a holographic interference pattern and a method of recording a holographic interference pattern using the apparatus, the apparatus and the method being capable of simplifying a process of aligning a light source and a photosensitive material in order to record a holographic interference pattern on a three-dimensional coordinate system and then realigning the light source and the photosensitive material in order to record a different holographic interference pattern.

Abstract: Disclosed is an automatic image classification and processing method based on the continuous processing structure of multiple artificial intelligence models. An automatic image classification and processing method based on a continuous processing structure of multiple artificial intelligence models includes receiving image data, generating a first feature extraction value by inputting the image data into a first feature extraction model among feature extraction models, generating a second feature extraction value by inputting the image data into a second feature extraction model among the feature extraction models, and determining a classification value of the image data by inputting the first and second feature extraction values into a classification model.

Abstract: An intersection right turn hazard warning method using an intersection entry guidance system of a subject vehicle reduces a collision hazard that may occur upon a right turn of the subject vehicle at an intersection. The method may include determining intersection information and vehicle right turn information from a vehicle information sensor, traffic light-blinking pattern information of left/right crosswalk traffic lights and a road-traveling traffic light from a first vehicle exterior information sensor. The method may also include determining longitudinal movement pattern information of an object at the intersection from a second vehicle exterior information sensor. The method May further include outputting an intersection scenario-specific warning to a human machine interface (HMI) and/or a surround view monitor (SVM) upon a right turn of the subject vehicle at the intersection according to an intersection scenario selected from a intersection situation classification table.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Abstract: A light emitting diode according to an exemplary embodiment of the present disclosure includes a first conductivity type semiconductor layer; an active region including a barrier layer and a well layer; a strain control layer disposed between the first conductivity type semiconductor layer and the active region; a superlattice layer disposed between the strain control layer and the active region; a second conductivity type semiconductor layer disposed on the active region; and an electron blocking layer disposed between the active region and the second conductivity type semiconductor layer, in which the first conductivity type semiconductor layer and the well layer are represented by a predetermined formula, and a ratio of a mole fraction of In to a mole fraction of Ga in the first conductivity type semiconductor layer and a ratio of a mole fraction of In to a mole fraction of Ga in the well layer satisfy a predetermined equation.

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A regenerative braking system is provided. The regenerative braking system includes: a preceding vehicle recognition module installed in a vehicle, the preceding vehicle recognition module configured to determine whether a preceding vehicle is present and measure information on a relative distance and a relative velocity to the preceding vehicle; a vehicle sensor installed in the vehicle; and a controller configured to receive information generated from the preceding vehicle recognition module and a sensor signal generated form the vehicle sensor; to generate a reference deceleration to maintain a distance from the preceding vehicle within a safety distance; to generate a driving torque command for outputting regenerative braking torque for following the generated reference deceleration; and to transfer the generated driving torque command to a vehicular driving system.

Abstract: A substrate processing apparatus including the controller are provided. The controller includes: a signal analyzer configured to detect at least one of an amplitude, phase, and frequency of a first signal, which is provided to a chamber; a radio frequency (RF) signal generator configured to generate an RF signal with a natural frequency based on a power of the first signal; a harmonic controller configured to generate a second signal based on the power of the first signal and at least one of the amplitude, phase, and frequency of the first signal, the second signal having a different amplitude, a different phase, and/or a different frequency from the RF signal; an operator configured to perform an operation on the RF signal and the second signal; and a filter configured to generate an RF control signal by filtering an output signal of the operator.

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.