Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

Abstract: Provided is a transparent substrate with a multilayer thin film coating, in which the multilayer thin film coating includes a lower dielectric layer, a lower protective layer, a metal functional layer having an infrared reflection function, an upper protective layer, and an upper dielectric layer, which are sequentially laminated on the transparent substrate, the thickness of the metal function layer is 12 nm or more, and the thickness of the lower protective layer is larger than that of the upper protective layer and the thickness of the lower protective layer is 2 nm or more.

Abstract: A double frame nanoparticle synthesis method includes: forming a first platinum layer of a closed loop structure on an edge region of a 2-dimensional gold nanoparticle; removing a portion of the gold nanoparticle in an exposed inner region thereof free of the first platinum layer, thereby forming a single frame structure; growing a first gold thin film on the single frame structure; forming a second platinum layer on inner and outer edge regions of the first gold thin film; removing a portion of the first gold thin film in an exposed region thereof free of the second platinum layer, thereby forming a double frame structure having an inner frame of a closed loop structure, and an outer frame having a closed loop structure surrounding the inner frame and partially connected to the inner frame; and forming a second gold thin film on a surface of the double frame structure.

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

Abstract: A system and method of calculating a vehicle DTE are provided to calculate a fuel efficiency of each vehicle drive mode, and display a more accurate DTE of each drive mode. The method includes when a driver selects a drive mode and a drive distance of the selected drive mode is accumulated while a vehicle is being driven in the selected mode, collecting drive data including an accumulated drive distance of each drive mode, and fuel efficiency information of each drive mode. A final fuel efficiency of each drive mode is calculated using a drive distance of each drive mode, a consumption energy of each drive mode or a fuel efficiency of each drive mode, and a learning fuel efficiency. A DTE of each drive mode is then calculated based on the calculated final fuel efficiency of each drive mode.

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract: A red light emitting device according to an embodiment of the present disclosure includes: a first conductivity type semiconductor layer; a second conductivity type semiconductor layer; and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, in which the first conductivity type semiconductor layer includes a plurality of protrusions on a surface thereof.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: A system and method for controlling charge and discharge using paddle braking, which is capable of improving energy efficiency of an entire system by scheduling other loads except for a drive motor and using some of the energy generated by regenerative braking to operate the loads according to the scheduling thereof without storing it in a battery, includes an input unit configured to input a braking command to a vehicle, a regenerative braking unit configured to perform driving and regenerative braking of the vehicle, a load unit including a plurality of other loads using electrical energy charged in a battery, and a control unit configured to receive the braking command and control braking and regenerative braking.

Abstract: An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.

Abstract: Provided is a multi-beam laser debonding apparatus for debonding an electronic component from a substrate, the apparatus including: a first laser module to emit a first laser beam to a predetermined range of a first substrate area including attachment positions of a debonding target electronic component and a neighboring electronic component to thereby heat a solder of the electronic components to reach a predetermined pre-heat temperature; and a second laser module to emit a second laser beam overlapping the first laser beam to a second substrate area smaller than the first substrate area, the second substrate area including the attachment position of the debonding target electronic component to thereby heat the solder of the debonding target electronic component to reach a debonding temperature at which the solder commences melting.

Abstract: An organic light emitting diode display device and a method for manufacturing the same are disclosed. The organic light emitting diode display device includes: a substrate having first and second subpixels, each of the first and second subpixels having an emission area; a thin film transistor in each of the first and second subpixels; a first anode connected to the thin film transistor and having a first area; and a second anode having a second area greater than the first area, wherein the second anode is disposed on the first anode to cover the first anode.

Abstract: The present invention relates to a method for forming an amorphous layer on one surface of a second substrate through a simple method of performing laser irradiation on a multilayered metal layer provided on a first substrate.

Abstract: A display apparatus can include at least one light-emitting device on a device substrate, an encapsulating element on the device substrate and covering the light-emitting device, an encapsulation substrate on the encapsulating element and including a metal, and a surface particle layer surrounding at least a portion of the encapsulation substrate. The surface particle layer can include metal particles dispersed at a surface of the encapsulation substrate. The surface particle layer can have a thermal conductivity that is higher than a thermal conductivity of the encapsulation substrate.

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.