Patents by Inventor Jae-young Park

Jae-young Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180337300
    Abstract: The present disclosure relates to an energy conversion material including: a pair of 2-dimensional active layers; and a property control layer positioned between the 2-dimensional active layers, and the property control layer is changed in any one or more of structure and state depending on an external environmental factor and performs reversible switching between the 2-dimensional active layers.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 22, 2018
    Applicant: Research & Business Foundation Sungkyunkwan University
    Inventors: Jaichan LEE, Sangwoo KIM, Bongwook CHUNG, Jae Young PARK, Tae Yun KIM
  • Patent number: 10135416
    Abstract: A composite electronic component includes a composite body in which a common mode filter and a multilayer ceramic capacitor array are coupled to each other, the common mode filter including a first body having a common mode choke coil, and the multilayer ceramic capacitor array including a second body in which a plurality of dielectric layers are stacked.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Sik Chong, Jae Young Park, Jong Young Kim, Woo Jin Choi
  • Patent number: 10122339
    Abstract: A composite electronic component includes a composite body in which a common mode filter and a multilayer ceramic capacitor array are coupled to each other, the common mode filter including a first body in which a common mode choke coil is disposed, and the multilayer ceramic capacitor array including a second body in which a plurality of dielectric layers are stacked.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: November 6, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Sik Chong, Jae Young Park, Jong Young Kim, Woo Jin Choi
  • Patent number: 10056491
    Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: August 21, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Hoon Jeong, Hong Bum Park, HanMei Choi, Jae Young Park, Seung Hyun Lim
  • Patent number: 10040253
    Abstract: A three-dimensional printing control apparatus comprises a control command generator configured to: generate a control command for outputting a three-dimensional object having a first shape, and generate, in response to a request for changing a shape of the three-dimensional object from the first shape to a second shape is received while performing a output work for the three-dimensional object, an additional control command for outputting a changed three-dimensional object having the second shape; and a control command transmitter configured to, in response to determining that it is possible to output the changed three-dimensional object through the output work, substitute the additional control command for the control command with respect to a non-printed portion of the three-dimensional object.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Sung-Ho Jang, In-Hyok Cha, Yong-Wook Jeong, Sang-Hoon Han, Kwang-Min Choi, Jae-Young Park
  • Patent number: 10035297
    Abstract: Disclosed are an apparatus and method of generating a bitmap of a 3D model. The apparatus for generating a bitmap of a 3D model includes a pixel column generator configured to divide a 3D space into a plurality of pixel columns parallel to an output direction of a 3D printer, an intersection point calculator configured to calculate intersection points between the plurality of pixel columns and the 3D model, a rasterizer configured to rasterize the pixel columns and determine a support material region in each of the rasterized pixel columns based on the intersection points; and a bitmap generator configured to generate the bitmap of the 3D model by merging the rasterized pixel columns.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Kwang-Min Choi, Sung-Ho Jang, Jae-Young Park, Sang-Hoon Han
  • Publication number: 20180206777
    Abstract: Disclosed herein are a penile tumescence diagnosis device and method. The penile tumescence diagnosis device includes: a plurality of ring sensors configured to measure a body part of a user and generate sensor-sensed information; and a processor configured to generate diagnostic information about the body part of the user based on the sensor-sensed information generated by the plurality of ring sensors. The plurality of ring sensors includes: a first ring sensor configured to have a first threshold length and be disposed on the body part to surround the body part in a ring shape; and a second ring sensor configured to have a second threshold length larger than the first threshold length and be disposed on the body part to surround the body part in a ring shape.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Inventors: Sung Roh Yoon, Jae Young Park, Sung Woon Choi
  • Patent number: 10014300
    Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
  • Patent number: 10000024
    Abstract: An apparatus for controlling 3D printing includes an output determiner configured to determine, after generating a first control command to output a 3D object, whether an additional 3D object is able to be output through an output task for the 3D object, and a control command generator configured to generate a second control command to output a not-yet-output part of the 3D object and the additional 3D object if it is determined that the additional 3D object is able to be output through the output task.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: June 19, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Sung-Ho Jang, In-Hyok Cha, Yong-Wook Jeong, Sang-Hoon Han, Kwang-Min Choi, Jae-Young Park
  • Patent number: 9870647
    Abstract: The specification of the instant application is amended. Submitted herewith is a Substitute Specification. The Substitute Specification complies with 37 C.F.R. §§1.52(a)-(b) and 1.125(b), and no new matter has been added to the Substitute Specification. Submitted herewith are clean and marked up versions of Substitute Specification in compliance with 37 C.F.R. §§1.121(b)(3) and 1.125(c). Entry of the Substitute Specification is respectfully requested.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Jae-Young Park, Sung-Ho Jang, Kwang-Min Choi, Sang-Hoon Han
  • Patent number: 9859376
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-ki Lee, Jae-Young Park, Dong-Hun Lee, Bon-Young Koo, Sun-Young Lee, Jae-Jong Han
  • Publication number: 20170358680
    Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.
    Type: Application
    Filed: January 31, 2017
    Publication date: December 14, 2017
    Inventors: Seong Hoon JEONG, Hong Bum PARK, HanMei CHOI, Jae Young PARK, Seung Hyun LIM
  • Publication number: 20170358457
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first fin structure which includes first semiconductor patterns and second semiconductor patterns stacked alternately on a substrate and extends in a first direction, forming an exposed first wire pattern group which includes the second semiconductor patterns by removing the first semiconductor patterns, heat-treating the exposed first wire pattern group, and forming a first gate electrode which surrounds the first wire pattern group and extends in a second direction different from the first direction.
    Type: Application
    Filed: January 26, 2017
    Publication date: December 14, 2017
    Inventors: Hwa Jin JANG, Jae Young PARK, Sun Young LEE, Ha Kyu SEONG, Han Mei CHOI
  • Publication number: 20170317084
    Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.
    Type: Application
    Filed: April 6, 2017
    Publication date: November 2, 2017
    Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
  • Publication number: 20170316879
    Abstract: A composite electronic component composed of a composite body including a capacitor and an electrostatic discharge (ESD) protection device coupled to each other. The capacitor includes a ceramic body in which a plurality of dielectric layers and internal electrodes are stacked with a respective dielectric layer therebetween. The ESD protection device includes first and second electrodes disposed on the ceramic body, a discharging part disposed between the first and second electrodes, and a protective layer disposed on the first and second electrodes and the discharging part. An input terminal disposed on a first end surface of the composite body and is connected to internal electrodes and the first and second electrodes. A ground terminal formed on a second end surface of the composite body and is connected to internal electrodes and the first and second electrodes.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Inventors: Jin Hwan KIM, Dae Bok OH, Jae Young PARK, Ichiro TANAKA, Chang Ho LEE
  • Patent number: 9781436
    Abstract: Provided are a system and method for transmitting cross-sectional images of a three-dimensional (3D) object and a transmitting apparatus for executing the same. A system for transmitting cross-sectional images of a 3D object includes a transmitting apparatus configured to search for a changed region between cross-sectional images of adjacent layers among a plurality of cross-sectional images generated by slicing the 3D object in a horizontal direction, and compress the cross-sectional images using information about the changed region and a receiving apparatus configured to receive the compressed cross-sectional images from the transmitting apparatus and restore the compressed cross-sectional images using the information about the changed region and cross-sectional image information of a layer lower than the layers desired to be restored.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 3, 2017
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Sung-Ho Jang, Kwang-Min Choi, Sang-Hoon Hang, Jae-Young Park
  • Patent number: 9777153
    Abstract: A polyalkylene carbonate resin composition with interpenetrating network structure includes an aliphatic polycarbonate obtained through a reaction of carbon dioxide with at least one epoxide compound selected from the group consisting of (C2-C10)alkylene oxide substituted or unsubstituted with halogen or alkoxy, (C4-C20)cycloalkylene oxide substituted or unsubstituted with halogen or alkoxy, and (C8-C20)styrene oxide substituted or unsubstituted with halogen, alkoxy, alkyl or aryl, at least one compound selected from a polyol compound, an epoxy compound and an acryl compound, and a curing agent for polymerization or networking.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 3, 2017
    Assignees: SK Innovation Co., Ltd., SK Global Chemical Co., Ltd.
    Inventors: Seung Gweon Hong, Jae Young Park, Hye Lim Kim, Ji Yeon Choi, Kwang Jin Chung, Myung Ahn Ok
  • Patent number: 9718959
    Abstract: Provided are an aliphatic polycarbonate-polyurethane composition and an aliphatic polycarbonate-polyurethane polymer using the same.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 1, 2017
    Assignees: SK Innovation Co., Ltd., SK Global Chemical Co., Ltd.
    Inventors: Ji Yeon Choi, Jae Young Park, Seung Gweon Hong, Tae Wook Kwon, Kwang Jin Chung
  • Patent number: 9696830
    Abstract: Provided is a method of manufacturing a transparent circuit substrate for a touch screen. The method may involve forming an electrode layer on a transparent substrate, stacking a light shielding layer on the transparent substrate such that the light shielding layer is located on an outside of the electrode layer, stacking a mask on the light shielding layer and the electrode layer, forming a conductive layer on the mask, forming connecting lines for connecting the electrode layer and connecting terminals by removing the mask and a portion of the conductive layer, and forming the connecting terminals on the light shielding layer such that the connecting terminals contact the connecting lines.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Han Kim, Yeong-Seop Lee, Seok-Hong Jeong, Myung-Sop Lee, Kyoung-Suk Oh, Jung-Hun Woo, Dong-Chul Lee, Jong-Hyun Yim, Sung-Il Jang, Yong-Gu Cho, Hyoung-Jun Go, Kyoung-Hun Kim, Jeong-Eun Kim, Hyeon-Beom Kim, Dae-Bin Noh, Jae-Young Park, Eun-Jin Baek, Chung-Hee Lee, Sung-Ho Jung, Jae-Wook Cho
  • Patent number: 9685473
    Abstract: A 4-color pixel image sensor having a visible color noise reduction function in a near infrared ray (NIR) pixel may include an active pixel region having a plurality of photodiodes, a plurality of first metal layers, a plurality of color filters, a first NIR pixel and a micro-lens, which are stacked, wherein the plurality of photodiodes are arranged in series and the plurality of color filters are formed to be adjacent to each other in series; an NIR optical black pixel region having a plurality of photodiodes and a second NIR pixel, which are stacked, wherein the plurality of photodiodes are arranged in series; and a visible optical black pixel region having a plurality of photodiodes, a second metal layer, a plurality of color filters and a micro-lens, which are stacked, wherein the plurality of photodiodes are arranged in series, and the plurality of color filters are formed to be adjacent to each other in series, wherein the active pixel region, the NIR optical black pixel region and the visible optical b
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 20, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jae Young Park, Won Ho Lee