Abstract: Provided are a marine concrete composition using dechlorination microorganisms capable of easily removing chlorine generated by seawater through an electrical method by allowing electrons emitted from electricity-generating microorganisms to flow through steel fibers incorporated into ultra-high-performance concrete (UHPC) or high-performance fiber reinforced concrete (HPFRCC) through a dechlorination microbial capsule carrier and capable of self-healing concrete crack sites through a self-healing microbial capsule carrier and is also capable of fundamentally solving the problem of reduced durability against salt damage of ultra-high-performance concrete or high-performance fiber reinforced concrete for application in marine construction environments through a dechlorination microbial capsule carrier, and a method for constructing a marine concrete structure using the same.

Abstract: The present disclosure relates to medical use of a compound of chemical formula 1 for treatment or prevention of pulmonary fibrosis. The present disclosure also relates to combination therapy with the compound of chemical formula 1 and nintedanib.

Abstract: The present invention provides: novel compounds capable of producing monomethyl fumarate after the compounds are administered; pharmaceutical compositions comprising same as active ingredients; and pharmaceutical uses thereof for treating or alleviating various diseases including immune system abnormalities, neurodegeneration, and/or inflammatory diseases.

Abstract: In one example, an electronic device includes a lower substrate comprising a lower substrate upper side and a lower substrate lower side, and an upper substrate comprising an upper substrate upper side and an upper substrate lower side. The electronic device also includes a first electronic component and a second electronic component coupled to the upper substrate upper side. A first device interconnect and a second device interconnect couple the lower substrate upper side to the upper substrate lower side. The electronic device also includes a connect die coupled to the lower substrate upper side that electrically couples the first electronic component to the second electronic component. Other examples and related methods are also disclosed herein.

Abstract: Provided are a graphene wire, a cable to which the graphene wire is applied, and a method of manufacturing the graphene wire. The graphene wire includes a catalytic metal wire and a graphene layer coated on a surface of the catalytic metal wire, and the catalytic metal wire includes a stranded cable in which at least two core wires are twisted around each other.

Abstract: Provided is an electric wire structure including a copper (Cu) electric wire extending in a direction; and a graphene coating layer formed on an outer portion of the Cu electric wire to surround the Cu electric wire, wherein the Cu electric wire includes Cu having a purity of 99.9% or greater.

Abstract: Provided are a graphene wire, a cable to which the graphene wire is applied, and a method of manufacturing the graphene wire. The graphene wire includes a catalytic metal wire and a graphene layer coated on a surface of the catalytic metal wire, and the catalytic metal wire includes a stranded cable in which at least two core wires are twisted around each other.

Abstract: Provided is an electric wire structure including a copper (Cu) electric wire extending in a direction; and a graphene coating layer formed on an outer portion of the Cu electric wire to surround the Cu electric wire, wherein the Cu electric wire includes Cu having a purity of 99.9% or greater.

Abstract: According to an aspect of an exemplary embodiment, there is provided a method of obtaining graphene, the method comprising: preparing a graphene forming structure of which a first graphene is formed on one surface and a second graphene is formed on another surface, and that comprises at least one metal catalyst member; disposing a first carrier and a second carrier on the first graphene and the second graphene, respectively; and removing the metal catalyst member by applying an etchant to a side surface of the graphene forming structure while winding up the first carrier and the second carrier by respectively rotating a pair of rolls formed to face each other.

Abstract: According to an aspect of an exemplary embodiment, there is provided a method of obtaining graphene, the method comprising: preparing a graphene forming structure of which a first graphene is formed on one surface and a second graphene is formed on another surface, and that comprises at least one metal catalyst member; disposing a first carrier and a second carrier on the first graphene and the second graphene, respectively; and removing the metal catalyst member by applying an etchant to a side surface of the graphene forming structure while winding up the first carrier and the second carrier by respectively rotating a pair of rolls formed to face each other.

Abstract: A method of manufacturing a multi-layer circuit layer is provided. One example method includes the steps of: preparing an upper substrate and a lower substrate, wherein each of the upper and lower substrates includes a carrier layer and a seed layer, which are detachably connected to each other; forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer; preparing a core substrate, wherein circuit patterns comprising a conductive material are formed on the core substrate; coupling the upper substrate, the core substrate, and the lower substrate by interposing adhesive members; detaching the carrier layer from the seed layer; etching the seed layer, wherein the seed layer is removed; and electrically connecting the first circuit patterns and the second circuit patterns to the third circuit patterns, respectively.

Abstract: A printed circuit board (PCB) and appertaining method of manufacturing are provided. The method includes: coating a metal layer on the entire surface of a substrate having an outer surface on which an interconnection pattern is formed; partially removing the metal layer from the surface of the substrate to form a window for a chip to be mounted therein and partially exposing the interconnection pattern to form a bonding finger; forming a first insulating layer on the metal layer by primarily anodizing the metal layer; electroplating a surface of the bonding finger by supplying power to the metal layer; and forming a second insulating layer disposed below the first insulating layer by entirely and secondarily anodizing the metal layer. A gold electroplating process can be performed without a lead wire, and an oxide layer formed by an anodizing process can protect circuits formed on the substrate and electrically insulate them.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 ?m and a width of the additional lead is wider than 20 ?m. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.

Abstract: A printed circuit board (PCB) and appertaining method of manufacturing are provided. The method includes: coating a metal layer on the entire surface of a substrate having an outer surface on which an interconnection pattern is formed; partially removing the metal layer from the surface of the substrate to form a window for a chip to be mounted therein and partially exposing the interconnection pattern to form a bonding finger; forming a first insulating layer on the metal layer by primarily anodizing the metal layer; electroplating a surface of the bonding finger by supplying power to the metal layer; and forming a second insulating layer disposed below the first insulating layer by entirely and secondarily anodizing the metal layer. A gold electroplating process can be performed without a lead wire, and an oxide layer formed by an anodizing process can protect circuits formed on the substrate and electrically insulate them.

Abstract: A method of manufacturing a multi-layer circuit layer is provided. One example method includes the steps of: preparing an upper substrate and a lower substrate, wherein each of the upper and lower substrates includes a carrier layer and a seed layer, which are detachably connected to each other; forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer; preparing a core substrate, wherein circuit patterns comprising a conductive material are formed on the core substrate; coupling the upper substrate, the core substrate, and the lower substrate by interposing adhesive members; detaching the carrier layer from the seed layer; etching the seed layer, wherein the seed layer is removed; and electrically connecting the first circuit patterns and the second circuit patterns to the third circuit patterns, respectively.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient ?upper of the upper part is defined by the Equation of ? upper = ? i = 1 n ? ? i × E i × v i ? i = 1 n ? E i × v i , where ?i is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.