Abstract: A display device including a display panel including gate and data line that cross each other; a first control signal generation unit generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit starting to count a number of clocks of a fixed-frequency clock signal based on a point of time at which a first state of the source output enable signal ends, and outputting a second gate output enable signal when the counted number of the clocks becomes equal to a reference value; and a gate driving unit controlling an outputting of a gate signal to the gate lines using the second gate output enable signal.

Abstract: A cavitation resistant polyurethane composition includes a first solution comprising a urethane prepolymer and a second solution. The urethane prepolymer is synthesized by a polymerization of about 60 to about 70 weight percent of an isocynate compound and about 30 to about 40 weight percent of a polyol. An average functional group number of the isocyanate compound is at least 2. The second solution includes about 90 to about 95 weight percent of a polyol having an average functional group number of at least 4, about 1 to about 3 weight percent of a nano-carbon, about 1 to about 3 weight percent of a colorant, about 1 to about 3 weight percent of a moisture absorbent, about 1 to about 3 weight percent of an anti-wear agent, and about 1 to about 3 weight percent of a defoaming agent.

Abstract: A cavitation resistant polyurethane composition includes a first solution comprising a urethane prepolymer and a second solution. The urethane prepolymer is synthesized by a polymerization of about 60 to about 70 weight percent of an isocynate compound and about 30 to about 40 weight percent of a polyol. An average functional group number of the isocyanate compound is at least 2. The second solution includes about 90 to about 95 weight percent of a polyol having an average functional group number of at least 4, about 1 to about 3 weight percent of a nano-carbon, about 1 to about 3 weight percent of a colorant, about 1 to about 3 weight percent of a moisture absorbent, about 1 to about 3 weight percent of an anti-wear agent, and about 1 to about 3 weight percent of a defoaming agent.

Abstract: A display device including a display panel including gate and data line that cross each other; a first control signal generation unit generating a source output enable signal and a first gate output enable signal in synchronization with a data enable signal modulated according to a spread frequency clock signal; a second control signal generation unit starting to count a number of clocks of a fixed-frequency clock signal based on a point of time at which a first state of the source output enable signal ends, and outputting a second gate output enable signal when the counted number of the clocks becomes equal to a reference value; and a gate driving unit controlling an outputting of a gate signal to the gate lines using the second gate output enable signal.

Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.

Abstract: A method and apparatus for displaying received data using a separate device that makes a user's receiving terminal, that has received only a unique code of data, transmit the unique code to a separate display device connected to the Internet, and which makes the display device access a server, in which the data is stored, and display the data corresponding to the unique code. The apparatus displays received data using a code generation unit for generating a first unique code that matches metadata received from a data server that stores the data and the metadata, a first communication unit for transmitting the first unique code to a receiving terminal, and a second communication unit for receiving a second unique code from a display device and transmitting the stored metadata that matches the first unique code to the display device if the first unique code corresponds to the second unique code.

Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

Abstract: A 2-arylmethylazetidine carbapenem derivative of formula (I) or a pharmaceutically acceptable salt thereof exhibits a wide spectrum of antibacterial activities against Gram-positive and Gram-negative bacteria and excellent antibacterial activities against resistant bacteria such as methicillinresistant Staphylococcus aureus (MRSA) and quinolone-resistant strains (QRS):

Abstract: Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

Abstract: Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

Abstract: Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and R is selected from C4-C24 alkyl, C4-C24 alkenyl, C4-C24 alkoxy, C8-C24 alkenoxy, substituted C4-C24 hydrocarbon, non-substituted C1-C4 hydrocarbon or substituted C1-C4 hydrocarbon; and, partially etching the filler filling the via and an interlayer dielectric to form a trench, which is connected to the via in the region where the dual damascene interconnections are to be formed. Then, the filler remaining in the via is removed, and the trench and the via are filled with an interconnection material to complete the dual damascene interconnections.

Abstract: A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

Abstract: A 2-arylmethylazetidine carbapenem derivative of formula (I) or a pharmaceutically acceptable salt thereof exhibits a wide spectrum of antibacterial activities against Gram-positive and Gram-negative bacteria and excellent antibacterial activities against resistant bacteria such as methicillinresistant Staphylococcus aureus (MRSA) and quinolone-resistant strains (QRS).

Abstract: A personal video recorder (PVR) apparatus, in which an advertisement is provided, includes a broadcasting signal receiver to receive a broadcasting signal transmitted from a broadcasting station, an electronic program guide (EPG) analyzer to analyze EPG information included in the broadcasting signal, an editor to edit certain advertisement data according to the analysis result of the EPG analyzer, and an outputter to output the broadcasting signal received by the broadcasting signal receiver and the advertisement data edited by the editor. With such a PVR apparatus an advertisement can be provided that suits the characteristics of a user and is displayed to the user at a set time.

Abstract: The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

Abstract: A method and apparatus for displaying received data using a separate device that makes a user's receiving terminal, that has received only a unique code of data, transmit the unique code to a separate display device connected to the Internet, and which makes the display device access a server, in which the data is stored, and display the data corresponding to the unique code. The apparatus displays received data using a code generation unit for generating a first unique code that matches metadata received from a data server that stores the data and the metadata, a first communication unit for transmitting the first unique code to a receiving terminal, and a second communication unit for receiving a second unique code from a display device and transmitting the stored metadata that matches the first unique code to the display device if the first unique code corresponds to the second unique code.

Abstract: There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer.

Abstract: A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.