Abstract: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines.

Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.

Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.

Abstract: An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.

Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

Abstract: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.

Abstract: A semiconductor device includes an insulation layer including a cell contact hole, and a switching device in the cell contact hole, at least a part of a top surface of the switching device being inclined with respect to an axial direction of the cell contact hole.

Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.

Abstract: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.

Abstract: A semiconductor phase-change memory device comprises a data line disposed on a semiconductor substrate and a data storage structure disposed under the data line and having a concave portion extending in a direction along the data line. A data contact structure is configured to contact the data storage structure, and having a lower portion filling the concave portion of the data storage structure and an upper portion surrounding at least a lower portion of the data line. Each of sidewalls of the data storage structure is disposed at substantially the same plane as a corresponding one of sidewalls of the upper portion of the data contact structure.

Abstract: Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

Abstract: In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

Abstract: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.

Abstract: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines.

Abstract: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.

Abstract: A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.

Abstract: A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.