Patents by Inventor Jae-Hee Oh
Jae-Hee Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136208Abstract: A light-emitting element transfer system includes raw film cutting device for forming a transfer member by cutting a raw film, a stretching device for stretching a transfer film with a plurality of light-emitting elements disposed thereon, a circuit board support member for supporting a circuit board and transport head for adsorbing the transfer member and transferring the light-emitting elements on the transfer film onto the circuit board by using the adsorbed transfer member.Type: ApplicationFiled: July 20, 2023Publication date: April 25, 2024Inventors: Jeong Won HAN, Chung Sic CHOI, Won Hee OH, Han Chun RYU, Jae Woo LEE
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Publication number: 20240136538Abstract: Disclosed is an ionomer for a high-temperature polymer electrolyte membrane fuel cell, which includes a phosphorus (P)-containing functional group having proton conductivity and partially contains fluorine in the main chain thereof.Type: ApplicationFiled: December 20, 2022Publication date: April 25, 2024Inventors: Won Jae Choi, Songi Oh, Da Hee Kwak, Ji Hoon Jang, Sung Hee Shin, Jae Suk Lee, Hye Min Oh, In Gyu Bak
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Publication number: 20230317596Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface; an active pattern extending in a first direction on the first surface of the substrate; a first source/drain contact including a first portion connected to a source/drain region of the active pattern, and a second portion extending from the first portion in the first direction or in a second direction intersecting the first direction; a power rail providing a voltage on the second surface of the substrate; a through electrode connected to the power rail and penetrating the substrate; and a landing pad connecting the through electrode and the second portion of the source/drain contact.Type: ApplicationFiled: February 8, 2023Publication date: October 5, 2023Inventors: Ji Hyung KIM, Jae Hee OH, Je Gwan HWANG, Jeong Hoon AHN
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Publication number: 20230170289Abstract: An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.Type: ApplicationFiled: July 8, 2022Publication date: June 1, 2023Inventors: Woo Seong JANG, Won Ji PARK, Jeong Hoon AHN, Jae Hee OH, Ji Hyung KIM, Shaofeng DING, Seok Jun HONG, Je Gwan HWANG
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Patent number: 9117595Abstract: An electronic component with terminal strips joined to end faces of external electrodes via a solder is characterized in that two plate-like supports of each terminal strip are formed by bending two plate-like parts projecting outward in a line-symmetrical manner from both side edges of a plate-like leg in the width direction such that at least tips of the thickness surfaces on the electronic component sides of the two plate-like parts are positioned below an external electrode of the electronic component, and the electronic component is supported from below by the tips of the thickness surfaces on the electronic component sides of the four plate-like supports. Slipping of the electronic component from both terminal strips due to melting of the solder can be suppressed in a reliable manner.Type: GrantFiled: August 29, 2013Date of Patent: August 25, 2015Assignee: TAIYO YUDEN CO., LTD.Inventors: Naoki Saito, Katsunosuke Haga, Jae Hee Oh
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Patent number: 8958229Abstract: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines.Type: GrantFiled: April 19, 2011Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Park, Jae-Hee Oh, Sung-Won Kim
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Patent number: 8791448Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.Type: GrantFiled: September 28, 2012Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-in Kim, Jae-hee Oh, Jun-hyok Kong, Sung-ho Eun, Yong-tae Oh
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Patent number: 8724411Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.Type: GrantFiled: October 3, 2011Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Young Kim, Ki Whan Song, Jae Hee Oh, Ji-Hyun Jeong
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Publication number: 20140063687Abstract: An electronic component with terminal strips joined to end faces of external electrodes via a solder is characterized in that two plate-like supports of each terminal strip are formed by bending two plate-like parts projecting outward in a line-symmetrical manner from both side edges of a plate-like leg in the width direction such that at least tips of the thickness surfaces on the electronic component sides of the two plate-like parts are positioned below an external electrode of the electronic component, and the electronic component is supported from below by the tips of the thickness surfaces on the electronic component sides of the four plate-like supports. Slipping of the electronic component from both terminal strips due to melting of the solder can be suppressed in a reliable manner.Type: ApplicationFiled: August 29, 2013Publication date: March 6, 2014Applicant: TAIYO YUDEN CO., LTD.Inventors: Naoki SAITO, Katsunosuke HAGA, Jae Hee OH
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Patent number: 8518790Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: GrantFiled: December 3, 2012Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-in Kim, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Publication number: 20130187119Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.Type: ApplicationFiled: September 28, 2012Publication date: July 25, 2013Inventors: Jung-in Kim, Jae-hee Oh, Jun-hyok Kong, Sung-ho Eun, Yong-tae Oh
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Memory devices including decoders having different transistor channel dimensions and related devices
Patent number: 8493769Abstract: An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.Type: GrantFiled: March 16, 2010Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-ho Eun, Jae-Hee Oh -
Publication number: 20130143382Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: ApplicationFiled: December 3, 2012Publication date: June 6, 2013Applicant: Samsung Electronics Co., LtdInventors: Jung-in KIM, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Patent number: 8384060Abstract: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.Type: GrantFiled: November 18, 2008Date of Patent: February 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Chang Ryoo, Jae-Hee Oh, Jung-Hoon Park, Hyeong-Jun Kim, Dong-Won Lim
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Publication number: 20130009125Abstract: A semiconductor device includes an insulation layer including a cell contact hole, and a switching device in the cell contact hole, at least a part of a top surface of the switching device being inclined with respect to an axial direction of the cell contact hole.Type: ApplicationFiled: June 26, 2012Publication date: January 10, 2013Inventors: Jong-hyun PARK, Jae-hee Oh, Kyu-sul Park
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Patent number: 8324067Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.Type: GrantFiled: March 1, 2010Date of Patent: December 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-in Kim, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
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Publication number: 20120092946Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.Type: ApplicationFiled: October 3, 2011Publication date: April 19, 2012Inventors: Jin-Young KIM, Ki Whan SONG, Jae Hee OH, Ji-Hyun JEONG
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Patent number: 8148193Abstract: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.Type: GrantFiled: September 20, 2011Date of Patent: April 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Park, Jae-Hee Oh
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Patent number: 8143610Abstract: A semiconductor phase-change memory device comprises a data line disposed on a semiconductor substrate and a data storage structure disposed under the data line and having a concave portion extending in a direction along the data line. A data contact structure is configured to contact the data storage structure, and having a lower portion filling the concave portion of the data storage structure and an upper portion surrounding at least a lower portion of the data line. Each of sidewalls of the data storage structure is disposed at substantially the same plane as a corresponding one of sidewalls of the upper portion of the data contact structure.Type: GrantFiled: December 14, 2009Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Park, Jae-Hee Oh, Sung-Ho Eun
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Patent number: 8120005Abstract: In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.Type: GrantFiled: August 19, 2009Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyun Park, Jae-Hee Oh, Se-Ho Lee, Won-Cheol Jeong