Patents by Inventor Jae-Hoon Kim

Jae-Hoon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250243062
    Abstract: A standalone precursor is for synthesizing nanomaterials such as boron nitride nanotubes. The standalone precursor includes a pillar. Pores and through-holes are defined in the pillar. Each of the through-holes extends continuously from a first opening on an outer surface of the standalone precursor to a second opening on the outer surface of the standalone precursor. The first opening is diametrically opposite to the second opening across the standalone precursor.
    Type: Application
    Filed: March 11, 2025
    Publication date: July 31, 2025
    Inventors: Jae Woo KIM, Eun Kwang PARK, Jae Hoon KIM, Ji Seung KIM, Tae Hyun JUNG
  • Publication number: 20250234743
    Abstract: A display device includes a first substrate including a base layer, a pixel definition layer above the base layer, and defining a first opening and a second opening, a first light-emitting layer in the first opening, and including an organic light-emitting material, and a second light-emitting layer in the second opening, and including a first quantum dot, and a second substrate above the first substrate, and including a base substrate, a barrier wall under the base substrate, and defining a first barrier wall opening overlapping the first opening, and a second barrier wall opening overlapping the second opening, a first functional layer in the first barrier wall opening, and including a polymer-based material, a moisture-absorbing layer in the first barrier wall opening for absorbing a moisture emitted from the polymer-based material, and a second functional layer in the second barrier wall opening, and including the polymer-based material.
    Type: Application
    Filed: September 5, 2024
    Publication date: July 17, 2025
    Inventors: JAESUNG LIM, JAE-HOON KIM, JAEKWON HWANG
  • Publication number: 20250230947
    Abstract: Provided is a duct connecting apparatus that is easily mounted on an air conditioner and an air conditioner including the same. The duct connecting apparatus that connects a duct to an inlet of an air conditioner includes a housing provided with an intake hole communicating with the duct and a discharge hole communicating with the inlet, a latch part provided on a lower end of the housing and configured to be seated and mounted on a lower edge of an edge defining the inlet, and a coupling part provided on the housing and configured to detachably couple the housing to an outer surface of the air conditioner.
    Type: Application
    Filed: January 6, 2025
    Publication date: July 17, 2025
    Inventors: Cha Hyun SUNG, Hyeon Ho JEONG, Jae Hoon KIM, In Jae LEE
  • Publication number: 20250214396
    Abstract: Vehicle thermal management system comprising a refrigerant line circulating through a compressor, a condenser, an expansion valve, a chiller; a cooling heat exchanger and a heating heat exchanger provided in an air conditioner case so as to cool air and heat air, respectively; a first coolant line passing through the heating heat exchanger and carrying out heat exchange with the condenser of the refrigerant line; a second coolant line passing through the cooling heat exchanger and carrying out heat exchange with the chiller of the refrigerant line; a radiator enabling heat exchange between a coolant and outdoor air; a third coolant line passing through the radiator and carrying out heat exchange with a battery of a vehicle; and a coolant valve part for controlling the flow of a coolant of the second coolant line so that the coolant flows in series through the chiller, the cooling heat exchanger, the battery.
    Type: Application
    Filed: June 20, 2023
    Publication date: July 3, 2025
    Inventors: Jae Hoon KIM, Hae Jun LEE
  • Patent number: 12331174
    Abstract: A laminated polyester film according to the present invention comprises: a core layer; and a sub-layer laminated on at least one surface of the core layer and containing a first particle and a second particle which are different components, wherein an average diameter of the first particle is 6 to 20 times of an average diameter of the second particle. Types, different properties, sizes, and contents of the first particle and the second particle are adjusted to solve the image blurring phenomenon and prevent a winding fault generated during processing and winding a final product. Therefore, workability and perfection of a final product can be increased and the defect rate can be decreased.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: June 17, 2025
    Assignee: TORAY ADVANCED MATERIALS KOREA INC.
    Inventors: Seung Hwan Lee, Young Ho Kim, Jae Hoon Kim, Jae Hee Seong
  • Patent number: 12321877
    Abstract: According to an embodiment, in a solution provision method and system: a target solution for a target factory is determined in a platform in which solutions for a smart factory, the solutions including at least one template, are registered; at least one target template corresponding to the target solution is revised according to an environment of the target factory; and the target solution, to which the revised target template is applied, is applied to the target factory.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: June 3, 2025
    Assignees: Korea Advanced Institute of Science and Technology, Aim System, Inc.
    Inventors: Heung Nam Kim, Jae Hoon Kim, Il Jung Kim, Hee Su Chae, Man Ki Kim, Sung Joon Byun, Byoung Hoon Jang
  • Publication number: 20250176399
    Abstract: A display device includes a substrate. A pixel electrode is disposed on the substrate. A bank layer covers lateral edges of the pixel electrode and includes openings defining a plurality of emission areas. A plurality of light-emitting structures is disposed on the pixel electrode. The plurality of light-emitting structures is disposed in the plurality of emission areas, respectively. A common electrode is disposed on the plurality of light-emitting structures and the bank layer. An organic functional layer is disposed on the common electrode and is disposed in the plurality of emission areas. The organic functional layer comprises polyacrylic acid.
    Type: Application
    Filed: May 23, 2024
    Publication date: May 29, 2025
    Inventor: Jae Hoon KIM
  • Patent number: 12302550
    Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: May 13, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Jae Jung, Jae Hoon Kim, Kwang-Ho Park, Yong-Hoon Son
  • Patent number: 12302579
    Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: May 13, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jae Hoon Kim, Kwang-ho Park, Hyunji Song, Gyeonghee Lee, Seungjae Jung
  • Patent number: 12269738
    Abstract: A standalone precursor is for synthesizing nanomaterials such as boron nitride nanotubes. The standalone precursor includes a pillar. Pores and through-holes are defined in the pillar. Each of the through-holes extends continuously from a first opening on an outer surface of the standalone precursor to a second opening on the outer surface of the standalone precursor. The first opening is diametrically opposite to the second opening across the standalone precursor.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 8, 2025
    Assignee: NAIEEL TECHNOLOGY INC.
    Inventors: Jae Woo Kim, Eun Kwang Park, Jae Hoon Kim, Ji Seung Kim, Tae Hyun Jung
  • Publication number: 20250109453
    Abstract: A non-oriented electrical steel sheet according to an embodiment of the present invention contains, by wt %: 3.1 to 3.8% of Si, 0.5 to 1.5% of Al, 0.3 to 1.5% of Mn, 0.01 to 0.15% of Cr, 0.003 to 0.08% of Sn, 0.003 to 0.06% of Sb, and a balance of Fe and inevitable impurities. The non-oriented electrical steel sheet according to an embodiment of the present invention includes a surface portion present from a surface of the steel sheet to 1/10 of a thickness of the steel sheet in a direction from the surface of the steel sheet toward an inside of the steel sheet, and a central portion, and when punching the non-oriented electrical steel sheet, a length of a plastically deformed portion may be 100 ?m or less. In this case, the plastically deformed portion refers to a length of a portion from a punched end portion where hardness of the surface portion exceeds 1.10 times that of the central portion.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 3, 2025
    Applicant: POSCO Co., Ltd
    Inventors: Jae-Hoon KIM, Su-Yong SHIN, Yunsu KIM
  • Publication number: 20250064867
    Abstract: The present invention relates to a method for improving muscle strength, and/or muscle mass by administering a composition containing as an active ingredient at least one selected from the group consisting of Akkermansia muciniphila cells, a culture thereof and a lysate thereof, and a method for preventing or treating muscle diseases where muscle strength and/or mass is weakened by sarcopenia, cachexia or muscle wasting.
    Type: Application
    Filed: September 18, 2024
    Publication date: February 27, 2025
    Applicant: KOREA RESEARCH INSTITUTE OF BIOSCIENCE AND BIOTECHNOLOGY
    Inventors: Chul-Ho LEE, Byoung-Chan KIM, Yong-Hoon KIM, Jung-Ran NOH, Jae-Hoon KIM, Kyoung-Shim KIM, Dong-Hee CHOI, Young-Keun CHOI, Dong-Ho CHANG, Haiyoung JUNG, Jung Hwan HWANG
  • Publication number: 20250056863
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Applicant: SK keyfoundry Inc.
    Inventors: Min Kuck CHO, Jae Hoon KIM, Seung Hoon LEE
  • Publication number: 20250046056
    Abstract: A conversion model construction device updates a generation module to process a first training image of a first type into a conversion image by using a separation outline module, updates the generation module to process the conversion image into a shape of a second training image of a second type by using a shape inference module, and trains the conversion model by updating the generation module such that the conversion image is determined as a real image by a discriminator module. The separation outline module separates a polygon of an input image from a background and distinguishes an outline, the shape inference module compares a border shape of a polygon included in the first image with a border shape of a polygon included in the second image and the discriminator module determines whether the input image is a real image or a fake image according to the set condition.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Inventors: Do-Nyun KIM, Yun Hyoung NAM, Tae-Yeon KIM, Jae Hoon KIM
  • Patent number: 12215403
    Abstract: A non-oriented electrical steel sheet according to an embodiment of the present invention includes, in wt %, Si: 1.5 to 4.0%, Al: 0.1 to 1.5%, Mn: 0.05 to 1.5%, Sn: 0.015 to 0.1%, P: 0.005 to 0.05%, Ga: 0.001 to 0.004%, and Bi: 0.0005 to 0.003%, and the balance of Fe and inevitable impurities. An area fraction of texture in a {118}//ND orientation is higher than that of texture in a {111}//ND orientation.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 4, 2025
    Assignee: POSCO
    Inventors: Hunju Lee, Jae-Hoon Kim, Seung-Gon Lee, Seung Il Kim
  • Patent number: 12216588
    Abstract: A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 4, 2025
    Assignee: SK hynix Inc.
    Inventors: Sung Woo Hyun, Hyeong Tak Ji, Myoung Seo Kim, Jae Hoon Kim, Eui Cheol Lim
  • Publication number: 20250035700
    Abstract: A test tray system for electronics, like photonics integrated circuit (PIC) structures, and a related method are disclosed. The test tray system includes at least one test tray. Each test tray includes a first section exposing a first electrical component to a high temperature, and a second section covered by a thermal protection element configured to prevent a second component from being exposed to the high temperature at the same time that the first electrical component is being exposed to the high temperature. The test tray system allows testing of the first component at a high temperature, e.g., 125° C., while protecting the second component from the high temperatures.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventor: Jae Hoon Kim
  • Publication number: 20250020337
    Abstract: A mobile apparatus includes a mobile portion, a cabin housing that is mounted to the mobile portion and defines a first space and a second space, and an air-conditioning apparatus installed in the second space and configured to cool or heat the first space, where a compressor, a condenser, an expansion device, and an evaporator are modularized in the air-conditioning apparatus.
    Type: Application
    Filed: October 11, 2023
    Publication date: January 16, 2025
    Inventors: Yeong Jun Kim, Hochan An, Yeonho Kim, Jeawan Kim, Hoyoung Jeong, Man Hee Park, Jae Yeon Kim, Gwi Taek Kim, Jae Hoon Kim
  • Patent number: 12176402
    Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 24, 2024
    Assignee: SK keyfoundry Inc.
    Inventors: Min Kuck Cho, Jae Hoon Kim, Seung Hoon Lee
  • Patent number: D1085387
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: July 22, 2025
    Assignee: HEPHZIBAH CO., LTD.
    Inventors: Cha Hyun Sung, Hyeon Ho Jeong, Jae Hoon Kim, In Jae Lee, Sil Ro Sung