Patents by Inventor Jaehyun YEON

Jaehyun YEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220068662
    Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Inventors: Kun FANG, Jaehyun YEON, Suhyung HWANG, Hong Bok WE
  • Patent number: 11258165
    Abstract: Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: February 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Chin-Kwan Kim, Jaehyun Yeon, Suhyung Hwang
  • Publication number: 20220053639
    Abstract: A package that includes a substrate and an electrical component coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, and a solder resist layer located over a surface of the at least one dielectric layer. The solder resist layer includes a first solder resist layer portion comprising a first thickness, and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The electrical component is located over the second solder resist layer portion.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 17, 2022
    Inventors: Kun FANG, Jaehyun YEON, Suhyung HWANG, Hyunchul CHO, Boyu TSENG
  • Patent number: 11239573
    Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 1, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Milind Shah, Chin-Kwan Kim, Jaehyun Yeon, Rajneesh Kumar, Suhyung Hwang
  • Publication number: 20210376493
    Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Milind SHAH, Chin-Kwan KIM, Jaehyun YEON, Rajneesh KUMAR, Suhyung HWANG
  • Patent number: 11183446
    Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jaehyun Yeon, Suhyung Hwang, Hong Bok We, Kun Fang
  • Publication number: 20210351488
    Abstract: A multi-core broadband printed circuit board (PCB) antenna and methods for fabricating such an antenna are provided. One example antenna implemented with a multi-core PCB generally includes a first core structure, a second core structure disposed above the first core structure, and one or more metal layers disposed above the second core structure or below the first core structure. The first core structure includes a first core layer, a first metal layer disposed below the first core layer, and a second metal layer disposed above the first core layer. The second core structure includes a second core layer, a third metal layer disposed below the second core layer, and a fourth metal layer disposed above the second core layer. The first core layer and the second core layer may have different thicknesses.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 11, 2021
    Inventors: Chaoqi ZHANG, Suhyung HWANG, Jaehyun YEON, Taesik YANG, Jeongil Jay KIM, Darryl Sheldon JESSIE, Mohammad Ali TASSOUDJI
  • Publication number: 20210345492
    Abstract: A device that includes a flexible printed circuit board (PCB), a package coupled to the flexible PCB, a first antenna device coupled to the flexible PCB, and a second antenna device coupled to the flexible PCB. The first antenna device is configured to transmit and receive a first signal having a first frequency. The second antenna device is configured to transmit and receive a second signal having a second frequency. The first antenna device may be coupled to a second surface of the flexible PCB, and the second antenna device is coupled to the second surface of the flexible PCB. The first antenna device may be coupled to a second surface of the flexible PCB, and the second antenna device is coupled to a first surface of the flexible PCB.
    Type: Application
    Filed: November 10, 2020
    Publication date: November 4, 2021
    Inventors: Jaehyun YEON, Suhyung HWANG, Rajneesh KUMAR, Jeahyeong HAN
  • Patent number: 11139224
    Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 5, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Chaoqi Zhang, Rajneesh Kumar, Li-Sheng Weng, Darryl Sheldon Jessie, Suhyung Hwang, Jeahyeong Han, Xiaoming Chen, Jaehyun Yeon
  • Publication number: 20210280959
    Abstract: A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Jeahyeong HAN, Rajneesh KUMAR, Suhyung HWANG, Jaehyun YEON, Mohammad Ali TASSOUDJI, Darryl Sheldon JESSIE, Ameya GALINDE
  • Patent number: 11101220
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 24, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Aniket Patil, Jaehyun Yeon
  • Patent number: 11075260
    Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 27, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Chin-Kwan Kim, Hong Bok We, Jaehyun Yeon
  • Patent number: 11043740
    Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 22, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Suhyung Hwang, Chin-Kwan Kim, Hong Bok We, Jaehyun Yeon
  • Publication number: 20210175152
    Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 10, 2021
    Inventors: Chaoqi ZHANG, Rajneesh KUMAR, Li-Sheng WENG, Darryl Sheldon JESSIE, Suhyung HWANG, Jeahyeong HAN, Xiaoming CHEN, Jaehyun YEON
  • Publication number: 20210091017
    Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.
    Type: Application
    Filed: May 8, 2020
    Publication date: March 25, 2021
    Inventors: Jaehyun YEON, Suhyung HWANG, Chin-Kwan KIM, Rajneesh KUMAR, Darryl Sheldon JESSIE
  • Publication number: 20210066197
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Hong Bok WE, Aniket PATIL, Jaehyun YEON
  • Publication number: 20210028539
    Abstract: Methods and apparatuses for enhancing antenna modules with flexible portion are presented. An apparatus includes an antenna module having a first portion, a first antenna on the first portion, a second portion, a second antenna on the second portion, and a flexible portion physically connecting the first portion and the second portion. The flexible portion is arrangeable such that the first antenna and the second antenna are oriented to receive radio frequency signals from different directions or to transmit the radio frequency signals to different directions. At least one radio frequency integrated circuit is on the first portion. The first antenna and the second antenna, via the flexible portion, share the radio frequency integrated circuit for radio frequency signal transmission or reception.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 28, 2021
    Inventors: Hong Bok WE, Jaehyun Yeon, Suhyung Hwang, Darryl Sheldon Jessie
  • Publication number: 20200365983
    Abstract: Methods and apparatuses for enhancing antenna modules with a shield layer. The apparatus includes an antenna module having an antenna layer. The antenna layer includes an antenna. The antenna module further includes a signal routing layer; a radio frequency (RF) communication component disposed on the signal routing layer; a shield cover encasing the RF communication component; and a shield layer. The antenna module further includes an antenna module side. The antenna module side includes a side of the signal routing layer and a side of the antenna layer. The shield layer covers a portion of the antenna module side such that at least a portion of the side of the antenna layer is uncovered.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 19, 2020
    Inventors: Suhyung HWANG, Chin-Kwan Kim, Hong Bok We, Jaehyun Yeon
  • Publication number: 20200219803
    Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.
    Type: Application
    Filed: December 21, 2019
    Publication date: July 9, 2020
    Inventors: Kuiwon KANG, Chin-Kwan KIM, Aniket PATIL, Jaehyun YEON
  • Publication number: 20200212545
    Abstract: Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Suhyung HWANG