Patents by Inventor Jaehyun YEON
Jaehyun YEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12293980Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.Type: GrantFiled: May 8, 2020Date of Patent: May 6, 2025Assignee: QUALCOMM INCORPORATEDInventors: Jaehyun Yeon, Suhyung Hwang, Chin-Kwan Kim, Rajneesh Kumar, Darryl Sheldon Jessie
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Publication number: 20250096051Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate includes a cavity; and an encapsulation layer located at least between the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Inventors: Jaehyun YEON, Kun FANG, Suhyung HWANG, Sang-Jae LEE, Rajneesh KUMAR, Manuel ALDRETE, Zhijie WANG, Seongho KIM
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Publication number: 20250098218Abstract: A thin film transistor includes a first gate electrode on a substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, a sidewall spacer on a side wall of the drain electrode, and a first source electrode provided on the other side of the first active layer and a sidewall of the sidewall spacer.Type: ApplicationFiled: July 2, 2024Publication date: March 20, 2025Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Eun PI, Seung Youl KANG, Yong Hae KIM, Joo Yeon KIM, Hee-ok KIM, Jaehyun MOON, Jong-Heon YANG, Himchan OH, Seong-Mok CHO, Ji Hun CHOI, Chi-Sun HWANG
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Patent number: 12126071Abstract: Multi-directional antenna modules employing a surface-mount antenna(s) to support antenna pattern mufti-directionality, and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and multiple antennas in the package substrate. To provide multi-directionality in antenna radiation patterns, a first antenna is provided that is coupled to the package substrate and oriented in a first plane, and a second antenna is provided that coupled to the package substrate and oriented in a second plane orthogonal to the first plane. In an example, the second antenna is packaged in an antenna package that includes external metal pads that when surface mounted to the package substrate, cause the second antenna to oriented in the second plane.Type: GrantFiled: March 1, 2022Date of Patent: October 22, 2024Assignee: QUALCOMM INCORPORATEDInventors: Jaehyun Yeon, Kun Fang, Suhyung Hwang, Hyunchul Cho
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Patent number: 12125742Abstract: A package that includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high-density interconnects located in the at least one dielectric layer and through a first surface of the at least one dielectric layer; a second plurality of high-density interconnects located in the at least one dielectric.Type: GrantFiled: September 20, 2021Date of Patent: October 22, 2024Assignee: QUALCOMM INCORPORATEDInventors: Hyunchul Cho, Kun Fang, Jaehyun Yeon, Suhyung Hwang
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Publication number: 20240339414Abstract: A hybrid core substrate with embedded components, and methods for making the same, are disclosed. In an aspect a hybrid core substrate comprises a rigid core, a first laminate layer structure disposed above and mounted to the top surface of the rigid core and having a cavity in which a first component is embedded, and a second laminate layer structure disposed above and mounted to a top surface of the first laminate layer structure and having at least one electrical connection to the first laminate layer structure and at least one electrical connection to the first component, a first plurality of contacts disposed on the top surface of the second laminate layer structure and electrically connected to the second laminate layer structure. In some aspects, at least one contact is electrically connected to the embedded component.Type: ApplicationFiled: April 6, 2023Publication date: October 10, 2024Inventors: Jaehyun YEON, Suhyung HWANG, Omar James BCHIR, Hyunchul CHO, Yeoil PARK
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Patent number: 11869833Abstract: A package that includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a first via interconnect and a first trace interconnect, wherein the first via interconnect is directly coupled to the first trace interconnect. The first via interconnect is coupled to the first trace interconnect without an intervening pad interconnect between the first via interconnect and the first trace interconnect.Type: GrantFiled: September 15, 2021Date of Patent: January 9, 2024Assignee: QUALCOMM INCORPORATEDInventors: Kun Fang, Jaehyun Yeon, Suhyung Hwang, Hyunchul Cho
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Patent number: 11823983Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises at least one dielectric layer; a plurality of interconnects comprising plurality of pad-on-pad interconnects, wherein the plurality of pad-on-pad interconnects is embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect comprising a first pad and a second pad coupled to the first pad. The package further comprising a solder resist layer located over the first surface of the substrate. The solder resist layer comprises a first solder resist layer portion comprising a first thickness; and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The second solder resist layer portion is located between the at least one dielectric layer and the integrated device.Type: GrantFiled: March 23, 2021Date of Patent: November 21, 2023Assignee: QUALCOMM INCORPORATEDInventors: Kun Fang, Jaehyun Yeon, Suhyung Hwang, Hong Bok We
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Publication number: 20230307817Abstract: Antenna modules employing a package substrate with a vertically-integrated patch antenna(s), and related fabrication methods. The antenna module includes a radiofrequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and an antenna(s) in the package substrate. The package substrate includes one or more patch antennas that are planar-shaped and vertically integrated in a plurality of metallization layers in the package substrate, behaving electromagnetically as a patch antenna. In this manner, the patch antenna(s) can be formed as a vertically-integrated structure in the package substrate with fabrication methods used for fabricating metal interconnects and vias (e.g., a micro via fabrication process) in package substrates.Type: ApplicationFiled: February 16, 2022Publication date: September 28, 2023Inventors: Suhyung Hwang, Kun Fang, Jaehyun Yeon, Chin-Kwan Kim, Taesik Yang
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Patent number: 11764489Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.Type: GrantFiled: January 4, 2022Date of Patent: September 19, 2023Assignee: QUALCOMM INCORPORATEDInventors: Milind Shah, Chin-Kwan Kim, Jaehyun Yeon, Rajneesh Kumar, Suhyung Hwang
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Publication number: 20230282959Abstract: Multi-directional antenna modules employing a surface-mount antenna(s) to support antenna pattern mufti-directionality, and related fabrication methods. The antenna module includes a radio-frequency (RF) IC (RFIC) package that includes one or more RFICs for supporting RF communications and a package substrate that includes one or more metallization layers with formed metal interconnects for routing of signals between the RFICs and multiple antennas in the package substrate. To provide multi-directionality in antenna radiation patterns, a first antenna is provided that is coupled to the package substrate and oriented in a first plane, and a second antenna is provided that coupled to the package substrate and oriented in a second plane orthogonal to the first plane. In an example, the second antenna is packaged in an antenna package that includes external metal pads that when surface mounted to the package substrate, cause the second antenna to oriented in the second plane.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Inventors: Jaehyun Yeon, Kun Fang, Suhyung Hwang, Hyunchul Cho
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Patent number: 11735804Abstract: A multi-core broadband printed circuit board (PCB) antenna and methods for fabricating such an antenna are provided. One example antenna implemented with a multi-core PCB generally includes a first core structure, a second core structure disposed above the first core structure, and one or more metal layers disposed above the second core structure or below the first core structure. The first core structure includes a first core layer, a first metal layer disposed below the first core layer, and a second metal layer disposed above the first core layer. The second core structure includes a second core layer, a third metal layer disposed below the second core layer, and a fourth metal layer disposed above the second core layer. The first core layer and the second core layer may have different thicknesses.Type: GrantFiled: May 11, 2020Date of Patent: August 22, 2023Assignee: QUALCOMM INCORPORATEDInventors: Chaoqi Zhang, Suhyung Hwang, Jaehyun Yeon, Taesik Yang, Jeongil Jay Kim, Darryl Sheldon Jessie, Mohammad Ali Tassoudji
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Publication number: 20230155273Abstract: A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.Type: ApplicationFiled: November 4, 2022Publication date: May 18, 2023Inventors: Jeahyeong HAN, Rajneesh KUMAR, Suhyung HWANG, Jaehyun YEON, Mohammad Ali TASSOUDJI, Darryl Sheldon JESSIE, Ameya GALINDE
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Patent number: 11637057Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.Type: GrantFiled: December 21, 2019Date of Patent: April 25, 2023Assignee: QUALCOMM INCORPORATEDInventors: Kuiwon Kang, Chin-Kwan Kim, Aniket Patil, Jaehyun Yeon
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Publication number: 20230093681Abstract: A package that includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high-density interconnects located in the at least one dielectric layer and through a first surface of the at least one dielectric layer; a second plurality of high-density interconnects located in the at least one dielectric.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Hyunchul CHO, Kun FANG, Jaehyun YEON, Suhyung HWANG
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Publication number: 20230078231Abstract: A package that includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a first via interconnect and a first trace interconnect, wherein the first via interconnect is directly coupled to the first trace interconnect. The first via interconnect is coupled to the first trace interconnect without an intervening pad interconnect between the first via interconnect and the first trace interconnect.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Inventors: Kun FANG, Jaehyun YEON, Suhyung HWANG, Hyunchul CHO
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Publication number: 20230014567Abstract: Package substrates employing integrated slot-shaped antenna(s), and related integrated circuit (IC) packages and fabrication methods. The package substrate can be provided in a radio-frequency (RF) IC (RFIC) package. The package substrate includes one or more slot-shaped antennas each formed from a slot disposed in the metallization substrate that can be coupled to the RFIC die for receiving and radiating RF signals. The slot-shaped antenna includes a conductive slot disposed in at least one metallization layer in the package substrate. A metal interconnect in a metallization layer in the package substrate is coupled to the conductive slot to provide an antenna feed line for the slot-shaped antenna. In this manner, the slot-shaped antenna being integrated into the metallization substrate of the IC package can reduce the area in the IC package needed to provide an antenna and/or provide other directions of antenna radiation patterns for enhanced directional RF performance.Type: ApplicationFiled: July 14, 2021Publication date: January 19, 2023Inventors: Jaehyun Yeon, Kun Fang, Suhyung Hwang, Hyunchul Cho
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Patent number: 11551939Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.Type: GrantFiled: September 2, 2020Date of Patent: January 10, 2023Assignee: QUALCOMM INCORPORATEDInventors: Kun Fang, Jaehyun Yeon, Suhyung Hwang, Hong Bok We
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Patent number: 11545425Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.Type: GrantFiled: October 8, 2020Date of Patent: January 3, 2023Assignee: QUALCOMM INCORPORATEDInventors: Kun Fang, Jaehyun Yeon, Suhyung Hwang, Hong Bok We
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Patent number: 11495873Abstract: A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.Type: GrantFiled: March 5, 2020Date of Patent: November 8, 2022Assignee: Qualcomm IncorporatedInventors: Jeahyeong Han, Rajneesh Kumar, Suhyung Hwang, Jaehyun Yeon, Mohammad Ali Tassoudji, Darryl Sheldon Jessie, Ameya Galinde