Abstract: Embodiments relate to a polishing pad, which comprises a window having a hardness similar to that of its polishing layer. Since the polishing pad comprises a window having a hardness and a polishing rate similar to those of its polishing layer, it can produce an effect of preventing scratches on a wafer during a CMP process. In addition, the polishing layer and the window of the polishing pad have a similar rate of change in hardness with respect to temperature, so that they can maintain a similar hardness despite a change in temperature during the CMP process.

Abstract: Embodiments relate to a porous polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polishing pad can be adjusted in light of the volume thereof. Thus, the plurality of pores have an apparent volume-weighted average pore diameter in a specific range, thereby providing a porous polishing pad that is excellent in such physical properties as polishing rate and the like.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; wherein R11 and R12 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R11 and R12 is fluorine, L is a C1-C5 alkylene group or —O—, R13 and R14 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R13 and R14 is fluorine, and n and m are each independently an integer from 0 to 20, with the proviso that n and m are not simultaneously 0.

Abstract: An embodiment relates to a polishing pad which is used in a chemical mechanical planarization (CMP) process and has excellent airtightness, wherein the polishing pad is excellent in airtightness of a window opening and thus can prevent water leakage that may occur during a CMP process.

Abstract: Provided is a polishing pad that comprises a plurality of first grooves that have a shape of geometric figures that share a center; and a plurality of second grooves that radially extend from the center to the outer perimeter, wherein the depth of the second grooves is equal to, or deeper than, the depth of the first grooves. It is possible for the polishing pad to rapidly discharge any debris generated during the polishing process to reduce such defects as scratches on the surface of a wafer.

Abstract: Embodiments relate to a leakage-proof polishing pad for use in a chemical mechanical planarization (CMP) process and a process for producing the same.

Abstract: The present invention provides a polishing pad, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad, the surface zeta potential and its ratio of the polishing surface are controlled to specific ranges according to the type of polishing slurry, whereby it is possible to improve the characteristics of scratches and surface defects appearing on the surface of the semiconductor substrate and to further enhance the polishing rate.

Abstract: An embodiment relates to a polishing pad which is used in a chemical mechanical planarization (CMP) process and has excellent airtightness, wherein the polishing pad is excellent in airtightness of a window opening and thus can prevent water leakage that may occur during a CMP process.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. According to the embodiments, it is possible to provide a polishing pad in which the average diameter of the plurality of pores contained in the polishing pad, the sphericity of the plurality of pores, and the volume ratio thereof are adjusted, thereby enhancing the polishing speed and reducing surface such defects as scratches and chatter marks appearing on the surface of a semiconductor substrate.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiments, the number average diameter (Da) and number median diameter (Dm) of a plurality of pores are adjusted to achieve a specific range of the Ed value (Equation 1). As a result, an excellent polishing rate and within-wafer non-uniformity can be achieved.

Abstract: The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes in its main chain a silane repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is about 40 or less wherein R11 and R12 are each independently hydrogen or C1-C10 alkyl groups, and n is an integer from 1 to 30.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; wherein R11 and R12 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R11 and R12 is fluorine, L is a C1-C5 alkylene group or —O—, R13 and R14 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R13 and R14 is fluorine, and n and m are each independently an integer from 0 to 20, with the proviso that n and m are not simultaneously 0.

Abstract: The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.

Abstract: Embodiments relate to a polishing pad, which comprises a window having a hardness similar to that of its polishing layer. Since the polishing pad comprises a window having a hardness and a polishing rate similar to those of its polishing layer, it can produce an effect of preventing scratches on a wafer during a CMP process. In addition, the polishing layer and the window of the polishing pad have a similar rate of change in hardness with respect to temperature, so that they can maintain a similar hardness despite a change in temperature during the CMP process.

Abstract: The embodiments relate to a porous polyurethane polishing pad and a process for preparing a semiconductor device by using the same. The porous polyurethane polishing pad comprises a urethane-based prepolymer and a curing agent, and has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 ?m, a specific gravity of 0.7 to 0.9 g/cm3, a surface hardness at 25° C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm2, an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 101 to 250 MPa measured from a polishing surface in direct contact with an object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 ?m.

Abstract: Provided is a polishing pad that comprises a plurality of first grooves that have a shape of geometric figures that share a center; and a plurality of second grooves that radially extend from the center to the outer perimeter, wherein the depth of the second grooves is equal to, or deeper than, the depth of the first grooves. It is possible for the polishing pad to rapidly discharge any debris generated during the polishing process to reduce such defects as scratches on the surface of a wafer.

Abstract: The embodiments relate to a porous polyurethane polishing pad and a process for preparing a semiconductor device by using the same. The porous polyurethane polishing pad comprises a urethane-based prepolymer and a curing agent, and has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 ?m, a specific gravity of 0.7 to 0.9 g/cm3, a surface hardness at 25° C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm2, an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 30 to 100 MPa measured from a polishing surface in direct contact with an object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 ?m.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.