Abstract: The present invention relates to a composition for treating, improving, or preventing Alzheimer's disease caused by ApoE4 gene mutation, the composition including Banha-Sasim-Tang as an active ingredient. The composition including Banha-Sasim-Tang as an active ingredient of the present invention and a treatment method exhibit excellent effects of reducing amyloid beta proteins and inhibiting deposition thereof, which are specific to Alzheimer's disease caused by ApoE4 gene mutation, thereby having high applicability as a specific composition for preventing, improving, or treating Alzheimer's disease caused by ApoE4 gene mutation.

Abstract: An embodiment of the present specification discloses a display device including a display panel including a display area and a non-display area adjacent to the display area and a metal dam disposed in the non-display area to surround at least three surfaces of the display panel. The display panel includes a substrate, a pixel driving circuit disposed on the substrate, and a light emitting element driven by the pixel driving circuit, the metal dam may be spaced a selected distance from an edge of the display panel, the metal dam may be formed of a plurality of metal layers connected through at least one hole, and the metal dam may include a first metal dam, a second metal dam, and a third metal dam that are disposed in the non-display area while surrounding at least three surfaces of the display area.

Abstract: A display apparatus according to an exemplary embodiment is disclosed. A display apparatus according to an exemplary embodiment includes a substrate having a bending region between an active area and a pad area. The display apparatus includes a planarization film on the active area and the pad area in the substrate. The display apparatus includes a first organic film coated on the planarization film, a second organic film coated on the first organic film, and a third organic film coated on the second organic film. The third organic film is formed such that an upper surface thereof is flattened in the active region. The display apparatus includes a plurality of light-emitting elements disposed on the third organic film.

Abstract: A mother substrate for a display panel and a display panel using the same are disclosed. A mother substrate for a display panel includes a conductive ring disposed in a non-display area outside the display area and surrounding each of the display areas, and one or more dummy pixel driving circuits disposed in a non-display area outside the display area. An electrostatic discharge (ESD) prevention structure inside the dummy pixel driving circuit can prevent defects of display panels due to ESD occurring in the manufacturing process of the display panel.

Abstract: An embodiment discloses a display apparatus. The display apparatus includes a plurality of first electrodes and a contact electrode disposed on a substrate. The display apparatus includes a plurality of light-emitting elements disposed on the plurality of first electrodes. The display apparatus includes a first optical layer disposed between the plurality of light-emitting elements. The display apparatus includes a second electrode disposed on the plurality of light-emitting elements. The second electrode includes a first area disposed on the plurality of light-emitting elements and a second area extending outward from the first optical layer and electrically connected to the contact electrode. A plurality of signal wires connected to the plurality of first electrodes are provided, the second area of the second electrode comprises protruding portions extending to at least one of areas between the plurality of signal wires, and one of the protruding portions is connected to the contact electrode.

Abstract: A display device includes a plurality of first electrodes and a contact electrode on a substrate; a plurality of light-emitting elements on the plurality of first electrodes; a first optical layer between the plurality of light-emitting elements; and a second electrode on the plurality of light-emitting elements, the second electrode including a first region that is on the plurality of light-emitting elements and a second region that extends past an end the first optical layer and is in contact with the contact electrode.

Abstract: A receiver circuit includes a first amplification stage and a second amplification stage. The first amplification stage is configured to generate a first output signal by differentially amplifying an input signal pair. The second amplification stage is configured to generate a second output signal by amplifying the first output signal. The receiver circuit is configured to deactivate the second amplification stage and then deactivate the first amplification stage.

Abstract: A mother substrate for a display panel and a display panel using the same are disclosed. The mother substrate comprises a plurality of display area including a plurality of light-emitting areas configured to receive light-emitting elements, a plurality of wirings, and a plurality of pads connected to the plurality of wirings; a conductive ring in a non-display area that surrounds the display area such that each of the display areas is surrounded by the conductive ring and electrically connected to the pads; a photoresist pattern covering the plurality of display areas and the non-display area; and a first metal layer covering the photoresist pattern. The conductive ring includes an electrostatic blocking area.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: A polishing composition includes abrasive particles, a pyrrolidone containing a hydrophilic group, a dispersing agent, a first dishing inhibitor including polyacrylic acid, and a second dishing inhibitor including a non-ionic polymer.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A polishing composition includes abrasive particles, a pyrrolidone containing a hydrophilic group, a dispersing agent, a first dishing inhibitor including polyacrylic acid, and a second dishing inhibitor including a non-ionic polymer.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Provided is a chemical mechanical polishing (CMP) apparatus that includes a swing unit installed apart from a platen, on which a CMP pad to be conditioned is placed, at a predetermined interval, a connector installed on an upper end of the swing unit at one end thereof in a perpendicular direction to the swing unit and pivoting around the swing unit above the CMP pad, a rotator rotatably installed on the other end of the connector, a CMP pad conditioner coupled to the rotator and conditioning the CMP pad when rotated, and a vibration meter installed on the connector and detecting vibrations to measure a vibration acceleration of the CMP pad conditioner, thereby predicting a wear rate of the CMP pad based on the vibration acceleration and a state in which the CMP pad conditioner is installed or being used.

Abstract: This invention relates to a conditioner for a CMP (Chemical Mechanical Polishing) pad, which is used in a CMP process which is part of the fabrication of a semiconductor device, and more particularly, to a CMP pad conditioner in which the structure of the cutting tips is such that the change in the wear of the polishing pad is not great even when different kinds of slurry are used and when there are changes in pressure of the conditioner, and to a method of manufacturing the same.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.