Patents by Inventor Jaewoong Sim

Jaewoong Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bypassing Memory Requests to a Main Memory
    Publication number: 20140164713
    Abstract: Some embodiments include a computing device with a control circuit that handles memory requests. The control circuit checks one or more conditions to determine when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory. When the memory request should be bypassed to a main memory, the control circuit sends the memory request to the main memory. Otherwise, the control circuit sends the memory request to the cache memory.
    Type: Application
    Filed: December 9, 2012
    Publication date: June 12, 2014
    Applicant: ADVANCED MICRO DEVICES
    Inventors: Jaewoong Sim, Gabriel H. Loh
  • Predicting Outcomes for Memory Requests in a Cache Memory
    Publication number: 20140143502
    Abstract: The described embodiments include a cache controller with a prediction mechanism in a cache. In the described embodiments, the prediction mechanism is configured to perform a lookup in each table in a hierarchy of lookup tables in parallel to determine if a memory request is predicted to be a hit in the cache, each table in the hierarchy comprising predictions whether memory requests to corresponding regions of a main memory will hit the cache, the corresponding regions of the main memory being smaller for tables lower in the hierarchy.
    Type: Application
    Filed: January 8, 2013
    Publication date: May 22, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, Jaewoong Sim
  • Bypassing a Cache when Handling Memory Requests
    Publication number: 20140143493
    Abstract: The described embodiments include a computing device that handles memory requests. In some embodiments, when a memory request is to be sent to a cache in the computing device or to be bypassed to a next lower level of a memory hierarchy in the computing device based on expected memory request resolution times, a bypass mechanism is configured to send the memory request to the cache or bypass the memory request to the next lower level of the memory hierarchy.
    Type: Application
    Filed: December 14, 2012
    Publication date: May 22, 2014
    Applicant: ADVANCED MICRO DEVICES
    Inventors: Gabriel H. Loh, Jaewoong Sim, James M. O'Connor
  • Dynamically Configuring Regions of a Main Memory in a Write-Back Mode or a Write-Through Mode
    Publication number: 20140143505
    Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode.
    Type: Application
    Filed: January 7, 2013
    Publication date: May 22, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Jaewoong Sim, Mithuna S. Thottethodi, Gabriel H. Loh