Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage or a third voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage or the third voltage. In some instances, the digit lines may be selected (e.g., driven) according to a pattern.

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a write pulse may be applied to one or more memory cells based on an associated memory device transitioning power states. To apply the wire pulse, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage or a third voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage or the third voltage. In some instances, the digit lines may be selected (e.g., driven) according to a pattern.

Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.

Abstract: A system includes a processor and a flash memory block that may receive an operating voltage sufficient for reading a memory cell. A standby oscillator may generate a first signal to a Power-Supply-In-Package block and a second, higher frequency signal to a regulator block. The first signal may control the time at which charge is stored on a first capacitor that may be used to provide charge in a standby mode to a second capacitor. The second signal may control the time at which charge is stored on the second capacitor.

Abstract: A system includes a processor and a flash memory block that may receive an operating voltage potential sufficient for reading a memory cell. A Power-Supply-In-Package (PSIP) block may adjust a supply voltage in accordance with received data values and be used to power the flash memory block.

Abstract: A system includes a processor and a flash memory block that may receive an operating voltage potential sufficient for reading a memory cell. A Power-Supply-In-Package (PSIP) block may adjust a supply voltage in accordance with received data values and be used to power the flash memory block.

Abstract: A system includes a processor and a flash memory block that may receive an operating voltage sufficient for reading a memory cell. A standby oscillator may generate a first signal to a Power-Supply-In-Package block and a second, higher frequency signal to a regulator block. The first signal may control the time at which charge is stored on a first capacitor that may be used to provide charge in a standby mode to a second capacitor. The second signal may control the time at which charge is stored on the second capacitor.

Abstract: A temperature measurement device includes at least one constant current generator to provide a first current and a second current to a temperature sensor, and a signal processing element to provide an analog output signal corresponding to a temperature of the temperature sensor based on a difference between a first voltage of the temperature sensor at the first current and a second voltage of the temperature sensor at the second current.

Abstract: What is disclosed is a system and method of generating a random frequency. First a fundamental noise signal from a fundamental noise source is detected. Then the fundamental noise signal is amplified. The amplified fundamental noise signal is then mixed with an oscillator signal. For one embodiment, the system is carried out in a single integrated circuit.

Abstract: A fingered capacitor in an integrated circuit. A first capacitor element is formed in a first layer of an integrated circuit (IC) die. The first capacitor element includes a positive plate and a negative plate. Each of the positive and negative plates of the first capacitor element has a plurality of fingers interdigitated with the fingers of the other of the positive and negative plates of the first capacitor element. The fingers are separated by a dielectric. The interdigitated fingers cooperate to generate fringe capacitance between neighboring fingers. A plurality of capacitor elements having interdigitated fingers can be provided in adjacent layers of the IC die.

Abstract: A signal generator in an integrated circuit includes circuitry to generate an output signal based on a supply signal and a difference between a first reference value and a second reference value. The output signal has an output signal variation due to at least one of a process variation, a temperature variation, and a variation in the supply signal. A first reference device provides the first reference value based on an input signal. A second reference device provides the second reference value based on the input signal. The second reference value can be any one of a plurality of selectable reference values. At least one of the plurality of selectable reference values reduces the output signal variation.

Abstract: A scaleable charge pump. The charge pump is configured on an integrated circuit device that operates at a supply voltage and includes a predetermined number of pump stages coupled in series, at least one of the stages being coupled to receive a first pumped clock signal. An output node coupled in series to one end of the predetermined number of series coupled pump stages provides a pumped output voltage.

Abstract: A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.

Abstract: A circuit for controlling the bias current in a differential amplifier is disclosed. A differential amplifier comprising complementary differential input transistor pairs includes variable bias current sources to provide bias currents to the differential input pairs. The variable bias current sources are coupled to an input current control unit that includes one or more programmable switches to vary the amount of bias current supplied to the differential input pairs. The slew rate, differential gain, and common mode input range of the differential amplifier may be varied by adjusting the bias currents to the differential input pairs. A cascode circuit is coupled between the differential input pairs and their respective load circuits to extend the common mode input range to the supply voltage rail values.

Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

Abstract: A negative voltage switching circuit in a nonvolatile memory includes a switching transistor coupled to an output of the negative voltage switching circuit and a first voltage source that has a voltage level substantially lower than zero volts. A pull-up circuit is coupled to a control terminal of the switching transistor and selectively to a second voltage source having a voltage level substantially above zero volts. The pull-up circuit applies the second voltage source to the control terminal of the switching transistor when the pull-up circuit is coupled to the second voltage source such that the switching transistor does not couple the first voltage source to the output. A pull-down circuit is coupled to the first voltage source and the control terminal of the switching transistor.

Abstract: A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.

Abstract: A method and apparatus for controlling a charge pump. A detection circuit is used to assert a detect signal when a power supply voltage exceeds a first threshold voltage and deassert the detect signal in response to a trigger. The detect signal is used to force a charge pump to operate in a mode that drives the capacitive node at its output to the target voltage with reduced latency. This is particularly useful for a device which may operate the charge pump in a reduced power mode which is designed to maintain the node voltage at reduced power rather than drive it to the degree necessary for reduced latency during power up.

Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.