Patents by Inventor Jahanshir J. Javanifard
Jahanshir J. Javanifard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5822246Abstract: A method and apparatus for detecting the power supply voltage level of a circuit. A control circuit is used to enable or disable a first voltage level detector circuit and a second voltage level detector circuit. The first voltage level detector circuit consumes less power than the second voltage level detector circuit. The first voltage level detector circuit is enabled during all user modes of operation. The second voltage level detector circuit is enabled during the normal or active mode of operation and during power-up in all user modes of operation. The second voltage level detector circuit may also be enabled during a reduced power mode of operation that does not consume the least amount of power. A select circuit selects the output from either the first voltage level detector or the second voltage level detector. The first voltage level detector circuit is selected during the user mode that consumes the least amount of power.Type: GrantFiled: September 30, 1996Date of Patent: October 13, 1998Assignee: Intel CorporationInventors: Mase J. Taub, Jahanshir J. Javanifard
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Patent number: 5781473Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pump are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.Type: GrantFiled: October 4, 1996Date of Patent: July 14, 1998Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Kerry D. Tedrow, Jin-Lien Lin, Jeffrey J. Evertt, Gregory E. Atwood
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Patent number: 5767735Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.Type: GrantFiled: October 3, 1996Date of Patent: June 16, 1998Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Kerry D. Tedrow, Jin-Lien Lin, Jeffrey J. Evertt, Gregory E. Atwood
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Patent number: 5732039Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.Type: GrantFiled: October 3, 1996Date of Patent: March 24, 1998Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Kerry D. Tedrow, Jin-Lien Lin, Jeffrey J. Evertt, Gregory E. Atwood
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Patent number: 5671179Abstract: A pulse generator circuit. The pulse generator circuit includes a first oscillator and a second oscillator coupled to the output of the first oscillator. The first oscillator is for outputting a first signal having a first frequency, and the second oscillator for outputting a second signal having a second frequency that is greater than the first frequency. The second signal is fed back to the second oscillator for controlling the operation of the second oscillator. The second oscillator is enabled to output the second signal in response to a rising edge of the first signal and disabled from outputting the second signal in response to a second edge of the second signal. To reduce power consumption of the pulse generator circuit, each of the oscillator circuits may be a ring oscillator comprising a plurality of inverters coupled in series and a feedback conductor coupled to the output of a last inverter and the input of a first inverter.Type: GrantFiled: December 11, 1996Date of Patent: September 23, 1997Assignee: Intel CorporationInventor: Jahanshir J. Javanifard
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Patent number: 5663918Abstract: An integrated circuit having internal power supplies includes circuitry for selecting either the external supply voltages or the internal power supplies to supply voltages to the remaining circuitry of the integrated circuit. The integrated circuit comprises voltage detector circuits for detecting the external voltage levels and a control circuit for selecting either the external supply voltages or the internal power supplies in response to the detected external voltages. The integrated circuit may be a flash EEPROM, and the external voltages may be the operating supply voltage VCC and the programming supply voltage VPP.Type: GrantFiled: December 19, 1995Date of Patent: September 2, 1997Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Kimberley D. Meister
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Patent number: 5602794Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.Type: GrantFiled: September 29, 1995Date of Patent: February 11, 1997Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Kerry D. Tedrow, Jin-Lien Lin, Jeffrey J. Evertt, Gregory E. Atwood
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Method and apparatus for sequential programming of the bits in a word of a flash EEPROM memory array
Patent number: 5537350Abstract: An integrated circuit arrangement for providing programming voltages to a flash EEPROM memory array including an arrangement for selecting subsets of bits of a word which is to be programmed and applying programming voltages only to the memory transistors of a selected subset.Type: GrantFiled: September 10, 1993Date of Patent: July 16, 1996Assignee: Intel CorporationInventors: Robert E. Larsen, Jahanshir J. Javanifard -
Patent number: 5524266Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.Type: GrantFiled: May 20, 1994Date of Patent: June 4, 1996Assignee: Intel CorporationInventors: Kerry D. Tedrow, Jahanshir J. Javanifard, Cesar Galindo
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Patent number: 5483486Abstract: A circuit for generating one of a plurality of output voltages. The circuit includes a first conductor coupled to a first supply voltage, a second conductor coupled to a second supply voltage, a charge pump having an input and an output, a multiplexor, a first regulation circuit, and a second regulation circuit. The first regulation circuit is coupled to the first input of the multiplexor and the output of the charge pump. The first regulation circuit is for generating a first regulation voltage in response to the first supply voltage and the output of the charge pump such that the charge pump outputs a first output voltage when the first input of the multiplexor is coupled to the output of the multiplexor. The second regulation circuit is coupled to the second input of the multiplexor and the output of the charge pump.Type: GrantFiled: October 19, 1994Date of Patent: January 9, 1996Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Marc E. Landgraf
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Patent number: 5455794Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.Type: GrantFiled: March 14, 1995Date of Patent: October 3, 1995Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Albert Fazio, Robert E. Larsen, James Brennan, Jr., Kerry D. Tedrow
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Patent number: 5446408Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.Type: GrantFiled: May 26, 1994Date of Patent: August 29, 1995Assignee: Intel CorporationInventors: Kerry D. Tedrow, Jahanshir J. Javanifard, Mase J. Taub
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Patent number: 5442586Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.Type: GrantFiled: September 10, 1993Date of Patent: August 15, 1995Assignee: Intel CorporationInventors: Jahanshir J. Javanifard, Albert Fazio, Robert E. Larsen, James Brennan, Jr., Kerry D. Tedrow
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Patent number: 5432469Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.Type: GrantFiled: May 24, 1994Date of Patent: July 11, 1995Assignee: Intel CorporationInventors: Kerry D. Tedrow, Jahanshir J. Javanifard, Cesar Galindo
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Patent number: 5426391Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.Type: GrantFiled: December 13, 1994Date of Patent: June 20, 1995Assignee: Intel CorporationInventors: Kerry D. Tedrow, Jahanshir J. Javanifard, Mase J. Taub
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Patent number: 5422586Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.Type: GrantFiled: September 10, 1993Date of Patent: June 6, 1995Assignee: Intel CorporationInventors: Kerry D. Tedrow, Jahanshir J. Javanifard, Cesar Galindo
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Patent number: 5317535Abstract: In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.Type: GrantFiled: June 19, 1992Date of Patent: May 31, 1994Assignee: Intel CorporationInventors: Sanjay S. Talreja, Duane Mills, Jahanshir J. Javanifard, Sachidanandan Sambandan
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Patent number: 5301161Abstract: A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider.Type: GrantFiled: January 12, 1993Date of Patent: April 5, 1994Assignee: Intel CorporationInventors: Marc E. Landgraf, Jahanshir J. Javanifard, Mark D. Winston
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Patent number: 5262990Abstract: A memory device includes a memory array and a plurality of output pins. A control input is provided for receiving a control signal. The control signal can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the memory device is in a first output mode. When the control signal is in the second voltage state, the memory device is in a second output mode. Circuitry is provided for selectively coupling the plurality of output pins to the memory array. An output mode select logic is coupled to receive the control signal for selecting the first output mode and the second output mode for the memory device. When the memory device is in the first output mode, the output mode select logic controls the circuitry to couple all of the plurality of output pins to the memory array. When the memory device is in the second output mode, the output mode select logic controls the circuitry to couple a portion of the plurality of output pins to the memory array.Type: GrantFiled: July 12, 1991Date of Patent: November 16, 1993Assignee: Intel CorporationInventors: Duane F. Mills, Jahanshir J. Javanifard, Rodney R. Rozman, Kevin W. Frary, Sherif R. B. Sweha