Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

Abstract: An image processing device including: a decision pixel manager for setting a decision area for a defect candidate pixel, and determining a first decision pixel and a second decision pixel, based on first phase information of pixels included in the decision area with respect to a first modulation frequency of a sensing light source among the pixels; a target pixel determiner for calculating a phase difference between the first decision pixel and the second decision pixel, based on second phase information of the pixels with respect to a second modulation frequency of the sensing light source, and determining the defect candidate pixel as a target pixel, corresponding to that the phase difference exceeds a predetermined reference value; and a phase corrector for changing a phase of the target pixel, based on the phase difference.

Abstract: A controller includes an e-fuse memory including a plurality of e-fuse memory cells and a control device. Such a control device may group the plurality of e-fuse memory cells into a plurality of e-fuse segments each having a given size, and set a plurality of e-fuse flags. Each of the plurality of e-fuse flags indicates whether data is programmed in a respective one of the plurality of e-fuse segment.

Abstract: A hardware accelerator includes a processing core including a plurality of multipliers configured to perform one-dimensional (1D) sub-word parallelism between a sign and a mantissa of a first tensor and a sign and a mantissa of a second tensor, a first processing device configured to operate in a two-dimensional (2D) operation mode in which results of computation by the plurality of multipliers are output, and a second processing device configured to operate in a three-dimensional (3D) operation mode in which results of computation by the plurality of multipliers are accumulated in a channel direction and then a result of accumulating the results of computation is output.

Abstract: The present disclosure relates to a fusion protein including a cell-penetrating peptide and an LRR domain derived from the NLRX1 protein. Since the fusion protein can effectively inhibit and alleviate the disease severity of autoimmune diseases and directly regulates T cell functions, it can be usefully used to treat or prevent autoimmune diseases.

Abstract: A novel cytokine-derived cell penetrating peptide and use thereof are provided. The cell penetrating peptide has the ability to effectively deliver a biologically active substance into phagocytes, particularly macrophages, both in vitro and in vivo. The cell penetrating peptide can deliver a biologically active substance into macrophages with high efficiency compared to TAT peptide and dNP2 peptide that are commercially available as cell penetrating peptides.

Abstract: The present invention provides a substrate processing apparatus including: a process chamber having a process space in which a substrate is processed; a substrate support including a susceptor having a plurality of pocket grooves recessed in a circumferential direction from a top surface with a circular plate shape so that the substrate is seated, a shaft configured to rotate the susceptor, and a satellite seated in the pocket groove and on which the substrate is seated; and a gas injection unit disposed at an upper portion of the process chamber to face the substrate support, thereby injecting a process gas toward the substrate support.

Abstract: The present disclosure relates to a composition for enhancing the cell permeability and gene correction efficiency of Cas protein and guide RNA. The currently used CRISPR-Cas-based gene correction technology has the problems of difficult intracellular injection in a complex form, unverified stability and low efficiency even after injection, and the off-target problem. In contrast, the composition for gene correction of the present disclosure can be usefully used for gene therapy due to remarkably high intracellular delivery efficiency, inhibited off-target, and ensured stability.

Abstract: The present disclosure relates to a fusion protein including a cell-penetrating peptide and an LRR domain derived from the NLRX1 protein. Since the fusion protein can effectively inhibit and alleviate the disease severity of autoimmune diseases and directly regulates T cell functions, it can be usefully used to treat or prevent autoimmune diseases.

Abstract: The present invention provides a substrate processing apparatus including: a process chamber having a process space in which a substrate is processed; a substrate support including a susceptor having a plurality of pocket grooves recessed in a circumferential direction from a top surface with a circular plate shape so that the substrate is seated, a shaft configured to rotate the susceptor, and a satellite seated in the pocket groove and on which the substrate is seated; and a gas injection unit disposed at an upper portion of the process chamber to face the substrate support, thereby injecting a process gas toward the substrate support.

Abstract: The present disclosure is directed to providing a new skin-penetrating peptide, a fusion product with a biologically active substance bound using the same, a cosmetic composition containing the same and a pharmaceutical composition for external application to skin containing the same. The skin-penetrating peptide of the present disclosure is less likely to cause an immune response as compared to existing skin-penetrating peptides and exhibits remarkably improved skin permeability. Therefore, the biologically active substance can be effectively delivered through the skin, particularly through the stratum corneum.

Abstract: The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Abstract: An error correcting method of a memory system includes: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fail chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.

Abstract: The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less insensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Abstract: The present disclosure is directed to providing a new skin-penetrating peptide, a fusion product with a biologically active substance bound using the same, a cosmetic composition containing the same and a pharmaceutical composition for external application to skin containing the same. The skin-penetrating peptide of the present disclosure is less likely to cause an immune response as compared to existing skin-penetrating peptides and exhibits remarkably improved skin permeability. Therefore, the biologically active substance can be effectively delivered through the skin, particularly through the stratum corneum.

Abstract: An operation method of a memory controller may include: performing a preset number of write operations on a redundancy region of a memory device, reading data of the redundancy region of the memory device, and detecting error bits which occur in the data, and generating an identifier corresponding to the memory device based on the detected error bits.

Abstract: An operation method of a memory controller may include: performing a preset number of write operations on a redundancy region of a memory device, reading data of the redundancy region of the memory device, and detecting error bits which occur in the data, and generating an identifier corresponding to the memory device based on the detected error bits.

Abstract: An error correcting method of a memory system may include: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fall chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.

Abstract: Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (MSB) N bits of a physical address for identifying the cubes; allocating least significant bit (LSB) M bits of the physical address for designating locations of memory cells included in each of the cubes, M and N being positive integers; storing information about a mapping between a logical address and the (M+N)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.

Abstract: Disclosed is an address mapping method of a memory system. The address mapping method may include grouping adjacent memory cells into multiple cubes, from a plurality of memory cells respectively located at intersections of a plurality of row lines and a plurality of column lines; allocating most significant bit (MSB) N bits of a physical address for identifying the cubes; allocating least significant bit (LSB) M bits of the physical address for designating locations of memory cells included in each of the cubes, M and N being positive integers; storing information about a mapping between a logical address and the (M+N)-bit physical address in a mapping table; and when the logical address in response to an external request is received, translating the logical address to the physical address based on the mapping table.