Patents by Inventor Jam-Wem Lee

Jam-Wem Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142950
    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Jam-Wem Lee, Kuo-Ji Chen, Kuan-Lun Cheng
  • Publication number: 20250125611
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20250107244
    Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Chu, Jam-Wem Lee, Wun-Jie Lin, Shou Ming Liu
  • Publication number: 20250098328
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped region in the substrate. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Tzu-Hao CHIANG, Wun-Jie LIN, Jam-Wem LEE
  • Patent number: 12255201
    Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chia Hsu, Tung-Heng Hsieh, Yung-Feng Chang, Bao-Ru Young, Jam-Wem Lee, Chih-Hung Wang
  • Publication number: 20250089379
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Inventors: Tao-Yi HUNG, Wun-Jie LIN, Jam-Wem LEE, Kuo-Ji CHEN
  • Publication number: 20250062138
    Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Tzu-Hsuan CHANG, Rong-Teng Lin, Bi-Xian Wu, Teng-Chin Hsu, Yun-Hong Yang, Chien-Liang Chen, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
  • Publication number: 20250038524
    Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 30, 2025
    Inventors: Jam-Wem Lee, Wun-Jie Lin, Chia-Jung Chang, Li-Wei Chu
  • Patent number: 12191655
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Patent number: 12183736
    Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Jam-Wem Lee, Kuo-Ji Chen, Kuan-Lun Cheng
  • Patent number: 12176341
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
    Type: Grant
    Filed: November 18, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Yi Hung, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
  • Patent number: 12166030
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped well in the substrate, wherein the doped well comprises a first concentration of dopants of a first type in the substrate. The semiconductor device further includes a doped region in the substrate, wherein the doped region comprises a second concentration of the dopants of the first type, the doped region extends around the doped well, and the doped region is electrically insulated from the doped well. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hao Chiang, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20240405012
    Abstract: An electrostatic discharge (ESD) protection cell region (of a semiconductor device) includes a resistor-diode ladder and a power clamp circuit coupled in parallel between a first power rail PR1 and a second power rail PR2. The resistor-diode ladder is also coupled between an input/output (I/O) pad of the semiconductor device and core circuitry of the semiconductor device. The resistor-diode ladder includes: a first diode coupled between a first node and the first power rail; a first resistor coupled between the first node and a second node; a second diode coupled between the second node and the first power rail; a third diode coupled between the first node and the second power rail; and a fourth diode coupled between the second node and the second power rail. The first node is coupled to the I/O pad. The resistor-diode ladder is coupled between the I/O pad and the core circuitry.
    Type: Application
    Filed: November 9, 2023
    Publication date: December 5, 2024
    Inventors: Li-Wei ChU, Jam-Wem LEE, Wun-Jie LIN, Shou Ming LIU
  • Publication number: 20240387511
    Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Jam-Wem LEE
  • Publication number: 20240387507
    Abstract: A method of making a semiconductor device includes manufacturing lines extending in a first direction over doped zones in a substrate, wherein each of the lines has a line width measured along a first direction. The method further includes trimming the lines into line segments having ends over an isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the first direction, and the line width is substantially similar to the gate electrode width.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Li-Wei CHU, Wun-Jie LIN, Yu-Ti SU, Ming-Fu TSAI, Jam-Wem LEE
  • Publication number: 20240387515
    Abstract: An integrated circuit (IC) device includes a substrate having a front side, a back side below the front side, and first functional circuitry and a first electrostatic discharge (ESD) clamp circuit on the front side of the substrate. The IC device further includes a first connection tower that extends below the back side of the substrate and is connected to an input/output pad below the back side of the substrate, and one or more first front side conductors and one or more first front side vias which connect the first buried connection tower to the first functional circuitry and to the first ESD clamp circuit.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE
  • Patent number: 12148746
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Hsu, Bo-Ting Chen, Jam-Wem Lee
  • Publication number: 20240371925
    Abstract: A semiconductor device includes a semiconductor substrate having a first protected circuit; a first guard ring; and a second guard ring adjacent to the first guard ring and around the first protected circuit. The second guard ring includes a first via tower configured to provide a first reference voltage; a second via tower configured to provide a second reference voltage different than the first reference voltage; and at least a third via tower configured to provide the first reference voltage.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Chia-Wei HSU, Bo-Ting CHEN, Jam-Wem LEE
  • Publication number: 20240363621
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Hung YEH, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20240347531
    Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Lin PENG, Han-Jen YANG, Jam-Wem LEE, Li-Wei CHU