Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer, and being coupled to the first voltage supply. The first diode is in the semiconductor wafer, and coupled between an IO pad and a first node. The second diode is in the semiconductor wafer, coupled to the first diode and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled between the first node and the second node, and further coupled to the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode and an ESD clamp circuit. The first diode is in a semiconductor wafer, and is coupled to an input output (IO) pad. The second diode is in the semiconductor wafer, and is coupled to the first diode and the TO pad. The ESD clamp circuit is in the semiconductor wafer, and is coupled to the first diode and the second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer. The first signal tap region is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor substrate having a first protected circuit, and forming a first guard ring around the first protected circuit including: forming a first wall configured to provide a first reference voltage; and forming a second wall configured to provide a second reference voltage different than the first reference voltage.

Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate, a first connection tower, and one or more first front side conductors and one or more first front side metal vias. The semiconductor substrate includes a first semiconductor substrate segment having first functional circuitry and a second semiconductor substrate segment having a first electrostatic discharge (ESD) clamp circuit. The first connection tower connects to an input/output pad. The one or more first front side conductors and one or more first front side metal vias connect the first buried connection tower to the first functional circuitry in the first semiconductor substrate segment and to the first ESD clamp circuit in the second semiconductor substrate segment.

Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

Abstract: A semiconductor device is provided. The semiconductor device comprises a detection circuit electrically coupled between a first node and a second node. The semiconductor device comprises a discharge circuit electrically coupled between the first node and a third node. The semiconductor device comprises a biasing circuit electrically coupled between the second node and the third node. The discharge circuit and the biasing circuit are configured to electrically conduct the first node and the second node in response to receiving a first signal from the detection circuit through a fourth node. A first voltage difference exists between the third node and the fourth node.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.