Abstract: A medical device is disclosed. The device may include a service component for use in detecting patient data, at least one processor coupled with the service component, a care protocol module executable by the at least one processor to provide healthcare to a patient at least in part by generating a request for processing by the service component, and a resource module executable by the at least one processor to manage access to the service component by identifying a level of service associated with the care protocol module and responding to the request by managing the service component to meet the level of service. The care protocol module implements a patient care protocol that includes a sequence of actions directed to the patient. The level of service indicates a level of performance that the patient care protocol requires of the resource module. Selective offloading of modular functions is also enabled.

Abstract: A method of installing a support member includes disposing a ground plate of a support member on a ground surface. The support member includes a lift assist component that engages with a bar connected to the ground plate. The method further includes adjusting a height of upper ends of the support member by actuating the lift assist component such that the upper ends of the support member are elevated or lowered.

Abstract: The invention features the use of a defined microbial consortia for the replacement of a gut microbiome associated with disease. In particular, the invention provides for the treatment of hyperammonemia, Clostridium difficile colitis, hepatic encephalopathy associated with cirrhosis, and inflammatory bowel disease.

Abstract: A method for ciphering protected content communicated between a first device and a plurality of devices over a plurality of channels comprises performing authentication between the first device and each of the plurality of devices to create two or more shared key and initialization vector pairs allowing the ciphering of the protected content; generating a key stream for each of the channels based on a selected one of the two or more of shared key and initialization vector pairs; maintaining a buffer for each channel, each of the buffer containing the key stream generated for the corresponding channel; and ciphering data incoming on a selected channel using the selected key stream from the buffer corresponding to the selected channel.

Abstract: An apparatus includes a first strap including an upper end and a lower end. A second strap is disposed adjacent to the first strap and includes an upper end and a lower end. The upper and lower ends of the second strap correspond in position with respect to the upper and lower ends of the first strap. A base portion connects the first and second straps between the respective lower ends of the first and second straps. A height adjustment system includes at least one bar disposed adjacent to at least one of the first and second straps, and a lift assist component that engages with the bar. In an orientation where the first and second straps extend vertically with respect to a horizontal plane, a distance between the horizontal plane and the respective upper ends of the first and second straps is adjustable via engagement between the lift assist component and the bar.

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Abstract: A system and method for communicating data between a first software and a second software located on first and second devices, respectively, has a hardware driver and memory associated with each device. Each communication of data from the first software to the second software allocates memory to manage data to be communicated from the first software to the second software, provides memory allocation information to the hardware driver associated with the first software, and transmits the data from the first hardware driver to the second hardware driver for delivery to the second software via the memory associated with the second software.

Abstract: A method for performing a cryptographic function on text to generate converted text comprises producing a random key stream having a first block size in a first frequency domain; converting the random key stream having a first block size in the first frequency domain to a random key stream in a second frequency domain; converting the random key stream having the first block size in the second frequency domain into smaller block sizes, thereby producing smaller block-sized random key stream of the second frequency domain; and converting the text using the smaller block-sized random key stream of the second frequency domain to produce the converted text. The frequency in the first frequency domain is preferably lower than the frequency in the second frequency domain.

Abstract: A method for performing a cryptographic function on text to generate converted text comprises producing a random key stream having a first block size in a first frequency domain; converting the random key stream having a first block size in the first frequency domain to a random key stream in a second frequency domain; converting the random key stream having the first block size in the second frequency domain into smaller block sizes, thereby producing smaller block-sized random key stream of the second frequency domain; and converting the text using the smaller block-sized random key stream of the second frequency domain to produce the converted text. The frequency in the first frequency domain is preferably lower than the frequency in the second frequency domain.

Abstract: A system for caching is configured for a pending lock state of a cache line, pre-loading the cache line into cache memory, and locking the cache line to prevent eviction of the cache line from the cache memory. The cache line is associated with instructions or data, and the pre-loading of the cache line may include loading the cache line into the cache memory before an algorithm relying on the instructions or data needs them. The pre-loading of a cache line associated with instructions may be done without execution of the instructions. The pending lock state of the cache line may be achieved by configuring the cache system to know that, when a cache line associated with an address is loaded into the cache memory, it should lock the cache line. The locking of the cache line may be done by promoting the pending lock state to a locked state.

Abstract: Methods, systems and apparatuses for a mediator enforcing policies to a resource utilizing an electronic content, are disclosed. One method includes receiving, by a mediator computing device of a mediator, a second share SKG2 from an owner server, wherein a first share SKG1 is provided to a member server of a member of a group by the owner server, wherein the owner defines policies associated with the group. The method further includes the mediator receiving a request from the member for mediation, including the mediator receiving a dispatch of the header of the encrypted electronic content, determining, by the mediator, whether the member is eligible to access the electronic content based at least in part on the policies associated with the group, if eligible, the mediator responds to the request for mediation with a member accessible header.

Abstract: A method of pairing an unregistered device with a virtual identity may include, at a first repository: receiving a request from the unregistered device, sending a pairing code and an identifier to the unregistered device, receiving the pairing code from a registered device, and sending the identifier to the registered device. The method may also include, at a second repository, receiving the pairing code and secret information from the registered device, receiving the pairing code in a transmission associated with the unregistered device, associating the unregistered device with the virtual identity using the pairing code, and sending the secret information to the unregistered device.

Abstract: A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification.

Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.

Abstract: Identifying the interactions of a selected cell across a hierarchical diagram of an integrated circuit and mapping the ways in which the cell can interact with other structures in the hierarchy reduces the computational load for design rule checking (DRC) and design rules for manufacturing (DRM). To this end, a cell and multiple instances of the cell are identified within hierarchical design levels of the chip. The interactions between the cell and other cells within the hierarchy are subtracted from the cell boundary, and the results of the subtracting are merged in the cell boundary. By subtracting the results of the merging, identical interactions are identified across the multiple instances of the cell. The results of the subtracting are used to generate a virtual hierarchical layer identical (VHLi) which aids in the simulation and verification of the chip.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a connector configured to electrically couple a device to the circuit board. The connector may include a conductive element configured to be electrically coupled to a first voltage and a detection pad configured to be electrically coupled to a second voltage via a resistor, such that when a device pin of a device is electrically coupled to the conductive element, the detection pad is electrically coupled to the conductive element via the device pin.

Abstract: Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.

Abstract: Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: There is disclosed a cache memory controller for storing cache data within a cache, the cache data comprising an unsecured version data to corresponding secured first data.