Patents by Inventor James A. Watson
James A. Watson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10043696Abstract: A wafer container utilizes a rigid polymer tubular tower with slots and a “getter” therein for absorbing and filtering moisture and vapors within the wafer container. The tower preferably utilizes a purge grommet at the base of the container and may have a check valve therein to control the flow direction of gas (including air) into and out of the container and with respect to the tower. The tower is sealingly connected with the grommet. The tower may have a getter media piece rolled in an elongate circular fashion forming or shaped as a tube and disposed within the tower and may have axially extending. The media can provide active and/or passive filtration as well as having capabilities to be recharged. Front opening wafer containers for 300 mm sized wafers generally have a pair of recesses on each of the left and right side in the inside rear of the container portions.Type: GrantFiled: July 21, 2014Date of Patent: August 7, 2018Assignee: Entegris, Inc.Inventors: James A. Watson, John Burns, Martin L. Forbes, Matthew A. Fuller, Mark V. Smith
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Publication number: 20150041360Abstract: A wafer container utilizes a rigid polymer tubular tower with slots and a “getter” therein for absorbing and filtering moisture and vapors within the wafer container. The tower preferably utilizes a purge grommet at the base of the container and may have a check valve therein to control the flow direction of gas (including air) into and out of the container and with respect to the tower. The tower is sealingly connected with the grommet. The tower may have a getter media piece rolled in an elongate circular fashion forming or shaped as a tube and disposed within the tower and may have axially extending. The media can provide active and/or passive filtration as well as having capabilities to be recharged. Front opening wafer containers for 300 mm sized wafers generally have a pair of recesses on each of the left and right side in the inside rear of the container portions.Type: ApplicationFiled: July 21, 2014Publication date: February 12, 2015Inventors: James A. WATSON, John BURNS, Martin L. FORBES, Matthew A. FULLER, Mark V. SMITH
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Patent number: 8783463Abstract: A wafer container utilizes a rigid polymer tubular tower with slots and a “getter” therein for absorbing and filtering moisture and vapors within the wafer container. The tower preferably utilizes a purge grommet at the base of the container and may have a check valve therein to control the flow direction of gas (including air) into and out of the container and with respect to the tower. The tower is sealingly connected with the grommet. The tower may have a getter media piece rolled in an elongate circular fashion forming or shaped as a tube and disposed within the tower and may have axially extending. The media can provide active and/or passive filtration as well as having capabilities to be recharged. Front opening wafer containers for 300 mm sized wafers generally have a pair of recesses on each of the left and right side in the inside rear of the container portions.Type: GrantFiled: March 13, 2009Date of Patent: July 22, 2014Assignee: Entegris, Inc.Inventors: James A. Watson, John Burns, Martin L. Forbes, Matthew A. Fuller, Mark V. Smith
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Publication number: 20110114534Abstract: A wafer container utilizes a rigid polymer tubular tower with slots and a “getter” therein for absorbing and filtering moisture and vapors within the wafer container. The tower preferably utilizes a purge grommet at the base of the container and may have a check valve therein to control the flow direction of gas (including air) into and out of the container and with respect to the tower. The tower is sealingly connected with the grommet. The tower may have a getter media piece rolled in an elongate circular fashion forming or shaped as a tube and disposed within the tower and may have axially extending. The media can provide active and/or passive filtration as well as having capabilities to be recharged. Front opening wafer containers for 300 mm sized wafers generally have a pair of recesses on each of the left and right side in the inside rear of the container portions.Type: ApplicationFiled: March 13, 2009Publication date: May 19, 2011Applicant: ENTEGRIS, INC.Inventors: James A. Watson, John Burns, Martin I. Forbes, Matthew A. Fuller, Mark V. Smith
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Patent number: 7512188Abstract: The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. The system comprises a first integrated circuit having an output circuit for generating phase shift keying signals and a second integrated circuit having an input circuit for decoding the phase shift keying signals. The output circuit may include a ring oscillator for generating multiple clock signals that are phase-locked to one another.Type: GrantFiled: April 10, 2003Date of Patent: March 31, 2009Assignee: Xilinx, Inc.Inventors: James A. Watson, Michael A. Margolese
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Patent number: 7349488Abstract: The present invention relates to a system for communicating between two integrated circuits (ICs) or within an IC. The ICs are either on the same circuit boards or on different circuit boards with a common backplane. A first integrated circuit has transmitter circuit that generates frequency shift keying signals using digital data and a second integrated circuit has a receiver circuit for recovering the digital data from the frequency shift keying signals.Type: GrantFiled: April 10, 2003Date of Patent: March 25, 2008Assignee: Xilinx, Inc.Inventors: Michael A. Margolese, James A. Watson
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Patent number: 7088288Abstract: A method of controlling an antenna system of a wireless communication network having a plurality of cells is disclosed. The method comprises the steps of determining antenna weights to enable communication between a wireless communication network and the wireless communication device within the wireless communication network; storing the antenna weights in a programmable memory associated with the wireless communication network; and providing predetermined stored antenna weights to the antenna system based upon a location of the wireless communication device. A circuit and wireless communication network for controlling an antenna system are also disclosed.Type: GrantFiled: January 10, 2003Date of Patent: August 8, 2006Assignee: Xilinx, Inc.Inventors: Michael A. Margolese, James A. Watson
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Patent number: 6897679Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: January 31, 2003Date of Patent: May 24, 2005Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Publication number: 20040066212Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: ApplicationFiled: January 31, 2003Publication date: April 8, 2004Applicant: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Publication number: 20030185401Abstract: A portable sound playing device is presented that can be used in any household or office setting, the sound playing device capable of playing masking sounds or music. This device is particularly useful in bathrooms for entertaining occupants or masking the sounds of bathroom activities. The functional housing can be both decorative and useful, coming in tissue dispenser, lotion dispenser, or stylish shapes.Type: ApplicationFiled: March 31, 2003Publication date: October 2, 2003Inventor: James A. Watson
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Publication number: 20020130681Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: ApplicationFiled: August 22, 2001Publication date: September 19, 2002Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6231103Abstract: A foldable motor vehicle seat including a horizontal seat cushion and a vertical seat back joined at a horizontal hinge for pivotal movement of the seat cushion from a horizontal position to a vertical position folded against the seat back. The seat back is connected to a side wall of a body of the motor vehicle for pivotal movement about a vertical axis between a seating position in a plane perpendicular to a longitudinal centerline of the motor vehicle and a cargo position in a plane parallel to the longitudinal centerline. With the seat cushion folded vertically against the seat back and the seat back in its cargo position, the floor of the motor vehicle under the seat is exposed for cargo. With the seat cushion horizontal and the seat back in its seating position, a passenger may sit on the foldable seat.Type: GrantFiled: March 15, 1999Date of Patent: May 15, 2001Assignee: General Motors CorporationInventors: Gerald Lee Elson, Elisabeth B. Nevitt, Gregory J. Cenzer, James A. Watson, Michael A. Jones, Robert W. Smith, Nancy M. Simioni, Michael H. Bates, Francis Nile Smith, Juan M. Capo
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Patent number: 6134173Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: November 2, 1998Date of Patent: October 17, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6109760Abstract: An illuminated power outlet assembly for a motor vehicle having an insulator and an illumination device. The illumination device includes a light emitting diode and a resistor electrically coupled in series. The illumination device is positioned within a power outlet, specifically between the casing and the insulator, such that when the illumination device illuminates, the light passes through the insulator to light the power outlet.Type: GrantFiled: December 14, 1998Date of Patent: August 29, 2000Assignee: DaimlerChrysler CorporationInventors: Ronald L. Salatrik, James A. Watson
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Patent number: 6064599Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs") The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: October 26, 1998Date of Patent: May 16, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6028808Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: May 6, 1997Date of Patent: February 22, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6023439Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: September 17, 1998Date of Patent: February 8, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6018490Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: October 9, 1998Date of Patent: January 25, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5982683Abstract: An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.Type: GrantFiled: March 23, 1998Date of Patent: November 9, 1999Assignee: Advanced Micro Devices, Inc.Inventors: James A. Watson, Fabiano Fontana, Jenny Chui, Steve Choi, Benjamin Lau
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Patent number: RE38651Abstract: A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.Type: GrantFiled: June 12, 1998Date of Patent: November 9, 2004Assignee: Altera CorporationInventors: Chiakang Sung, Wanli Chang, Joseph Huang, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Bahram Ahanin