Abstract: A system and method for making and using integrated circuits using a modeling system. The system utilizes a pin test buffer. The pin test buffer inputs external inputs to a pin, and outputs to the same pin from the device. If contention is noted between the system inputs to the pin, and outputs from the device to the pin, contention error notices are provided to the user.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A reprogrammable logic device and method of operation. The logic device is divided into a first hemisphere 101 and a second hemisphere 102. The first and second hemispheres of the arrays are internally connected by horizontal 20 and vertical 22 conductors. A global interconnect array 107 is placed between the hemispheres and is used to selectively connect the horizontal conductors of the hemispheres.

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

Abstract: A method and apparatus for predict-ahead pulse-to-pulse voltage control in a pulsed power supply system is disclosed. A DC power supply network is coupled to a resonant charging network via a first switch. The resonant charging network is coupled at a node to a storage capacitor. An output load is coupled to the storage capacitor via a second switch. A de-Q-ing network is coupled to the resonant charging network via a third switch. The trigger for the third switch is a derived function of the initial voltage of the power supply network, the initial voltage of the storage capacitor, and the present voltage of the storage capacitor. A first trigger closes the first switch and charges the capacitor. The third trigger is asserted according to the derived function to close the third switch. When the third switch is closed, the first switch opens and voltage on the node is regulated. The second trigger may be thereafter asserted to discharge the capacitor into the output load.

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

Abstract: A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

Abstract: A new slew rate controlled output buffer with built-in temperature and voltage compensation for integrated circuits is designed to reduce VCC/VSS switching noise encountered in high speed, high current drive integrated circuit applications.

Abstract: A vehicle steering column control cable mounting clip for an automatic transmission indicator dial system permitting the indicator pointer to be readily aligned with the dial indicia. The system includes a curvilinear looped flexible plastic tubular conduit having one end molded to the indicator housing and its other end molded to an adjustment slide selectively movable on a tongue portion of the clip by means of an adjustment screw interconnecting the slide and the clip. A flexible cable is slidable within the shielding conduit having one unshielded end connected to a pointer carrier and its other unshielded end fixed to a column rotatable shift tube actuator arm extending through an aperture in the column outer jacket. The clip has a pair of spring legs adapted for snap-in reception into the column jacket aperture and includes an integrally hinged lock-bar operative for positively capturing the clip in the aperture.