Abstract: An apparatus to store electrical energy has a first magnetic unit, a second magnetic unit, and a dielectric section. The first magnetic unit has a first magnetic section and a second magnetic section. The second magnetic unit has a third magnetic section and a fourth magnetic section. The dielectric section is configured between the first magnetic unit and the second magnetic unit. The dielectric section is arranged to store electrical energy, and dipoles of the first magnetic section, the second magnetic section, the third magnetic section, and the fourth magnetic section are arranged to prevent electrical energy leakage.

Abstract: A magnetic transistor circuit representing the data ‘1’ and ‘0’ of the binary system comprises a routing line and a magnetic transistor unit. The routing line has a current going through with a first current direction or a second current direction, wherein the first current direction and the second current direction are opposite to represent the data ‘1’ and the data ‘0’ respectively. The magnetic transistor unit couples to the routing line at an output end to control the direction of the current going through the routing line.

Abstract: A magnetic OR/NAND circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘OR’ and ‘NAND’ logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

Abstract: A magnetic transistor circuit with the AND, NAND, NOR and OR functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors act as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The AND, NAND, NOR and OR logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The EXOR logic function of the binary system can be implemented by the control of these metal devices.

Abstract: A single chip has a substrate and at least one magnetoresistive memory layer. The substrate has an underlying memory and a control circuit. The magnetoresistive memory layer is placed on the substrate, and has a plurality of magnetoresistive random access memory cells controlled by the control circuit.

Abstract: A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a third magnetic section and a fourth magnetic section, wherein the third magnetic section couples to a low voltage end, and the fourth magnetic section couples to the second magnetic section of the first magnetic transistor. The third magnetic transistor has a fifth magnetic section and a sixth magnetic section, wherein the fifth magnetic section couples with the second magnetic section and the fourth magnetic section together, and the sixth magnetic section couples to an input/output end.

Abstract: A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The buffer and inverter logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.