Abstract: A semiconductor device having a thin-film transistor (22) and a process for making the device. The semiconductor device includes a substrate (11) having a principal surface. A gate electrode (29) overlies the principal surface and a gate dielectric layer (23) overlies the gate electrode (29). A conductive channel interface layer (25) overlies the upper surface of the gate electrode (29) and is spaced apart from the gate electrode (29) by the gate dielectric layer (23). A conductive thin-film layer (57) overlies the gate electrode (29) and forms a metallurgical contact to the channel interface layer (25). Remaining portions of the thin-film overlie the principal surface and form source and drain regions (63, 65) of the thin-film transistor (22). The thin-film source and drain regions (63, 65) are formed by placing a diffusion barrier cap (60) over the channel portion (61) of the thin-film layer (57) and introducing conductivity determining dopant into the thin-film layer (57).

Abstract: A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

Abstract: A method for forming a grown bipolar transistor electrode contact wherein a substrate (12) is provided. A doped region (31) is formed within the substrate (12). A dielectric layer (26) is formed having an opening (36) which exposes a portion of the doped region (31). Conductive spacers (38) are formed adjacent a sidewall of the dielectric layer (26). A conductive region (34) is formed through either a selective process or an epitaxial process by using the conductive spacers (38) as a source for epitaxial or selective formation. The conductive region (34) forms the grown bipolar electrode contact by electrically contacting the doped region (31). The conductive region (34) is optionally overgrown in a lateral direction over a top surface of the dielectric layer (26) to form a self-aligned electrical contact pad for the doped region (31).

Abstract: A bipolar transistor (10) with reduced substrate trenching and reduced base electrode size. A substrate (12) is provided with an overlying first dielectric layer (20), an overlying first conductive layer (24), an overlying second dielectric layer (26), and a doped collector region (14, 16, and 18). An opening is formed within the layers (20, 24, and 26) forming a sidewall of conductive layer (24). A doped base diffusion (28) is formed within a portion of the substrate (12) exposed by the opening. A conductive grown region (30) is formed laterally adjacent the sidewall of conductive layer (24) and overlies substrate (12). A spacer (32) is formed adjacent a first portion of the conductive grown region (30). A second portion of the conductive grown region (30) is removed forming an exposed portion of substrate (12). A second spacer (36) is formed adjacent spacer (32). A conductive layer (38), which forms a doped emitter region is formed overlying the exposed portion of substrate (12).

Abstract: A vertical bipolar transistor (10) and a lateral bipolar transistor (11) are formed wherein both transistors (10 and 11) have a substrate (12). A dielectric layer (22) is formed overlying the substrate (12), and a conductive layer (24) is formed overlying the dielectric layer (22). Another dielectric layer (26) is formed overlying the conductive layer (24). A device opening is formed through the dielectric layers (22 and 26) and the conductive layer (24). A conductive region (33) is formed within the device opening and overlying the substrate (12). For transistor (10), the conductive region (33) is doped to form an active base electrode region (36) and a first current electrode region (38). A second current electrode region is formed via a diffusion (16). For transistor (11), a base electrode is formed via a diffused base region (46), and first and second current electrodes are respectively formed via diffused regions (44 and 48).

Abstract: A bipolar transistor having an inverse-T emitter electrode is formed in a semiconductor device (10) to reduce hot carrier injection (HCI) damage under reverse-biasing conditions and to increase emitter-base breakdown voltages. The bipolar transistor includes an emitter electrode having a central body portion (26) and shelf portions (38). Beneath the emitter electrode is an emitter region (30) and an active base region (25). Extrinsic base regions (35 and 36) are self-aligned to the shelf edges and are linked to the ative base region by link regions (27 and 28). Having the emitter-base junction beneath the shelf portions, and therefore under direct control of the emitter electrode, decreases the electrical field at the junction, which lessens HCI damage and improves breakdown characteristics. The inverse-T emitter electrode also eliminates the need to etch a polysilicon emitter electrode selective to an underlying silicon substrate.

Abstract: A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).

Abstract: A semiconductor device (10) has a bipolar transistor merged with an MOS transistor, the two transistors being separated essentially by a sidewall spacer and the bipolar transistor being self-aligned to the MOS transistor. The MOS transistor includes a gate (22) and a sorce region (38). A drain region of the MOS transistor is also an active base region (27) of the bipolar transistor. The bipoloar transistor further includes a first emitter region (40) formed in the active base region and a second emitter region (32) which is formed on the first emitter region and partially overlies the MOS transistor gate. The second emitter region is separated from the gate by a sidewall spacer (29) and an overlying dielectric layer (23).

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used as an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used to mask for a second ion implantation.

Abstract: A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is formed in the substrate extending from the first surface and a lightly doped epitaxial layer overlies the first surface. An isolation region is formed in the epitaxial layer dividing the epitaxial layer into an active surface region and an isolation region. A base electrode is formed on a first portion of the active surface region having an opening which exposes a second portion of the active surface region. An emitter electrode, which is self-aligned to the base electrode, overlies a portion of the base electrode and extends through the opening in the base electrode making contact with the second portion of the active surface region.

Abstract: The invention provides a method for patterning a submicron opening in a layer of semiconductor material. The method comprises use of conventional photolithography to position a sidewall spacer in a predetermined location on a semiconductor device. A layer of cobalt is selectively reacted with an underlying layer to form an image reversal layer which functions as a hard mask. The submicron features are then transferred into the underlying layer of semiconducting material by etching.

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used a mask for a second implantation.