Abstract: This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Abstract: A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel. The produced internal start pulse was qualified by an output of a last cell of the gate driver shift register. Other embodiments are also described and claimed.

Abstract: A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.

Abstract: This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel.

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Abstract: A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel. The produced internal start pulse was qualified by an output of a last cell of the gate driver shift register. Other embodiments are also described and claimed.

Abstract: A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.

Abstract: Embodiments for methods, apparatus and systems for operating a voltage regulator are disclosed. One embodiment of the voltage regulator generates a switching voltage through controlled closing and opening of a series switch element and a shunt switch element. The voltage regulator further includes a switched output filter that includes a plurality of capacitors for filtering the switching voltage and generating an output voltage. A mode controller is operative to disconnect at least one of the plurality of capacitors upon receiving a first indicator, where disconnecting causes the at least one of the plurality of capacitors to electrically float, wherein while the at least one capacitor is disconnected the output voltage is changed from a first value to a second value, return the output voltage to a first value or a third value upon receiving a second indicator, and reconnect the at least one of the plurality of capacitors.

Abstract: Embodiments for at least one method and apparatus of generating a regulated voltage are disclosed. One method includes generating the regulated voltage through controlled closing and opening of a series switch element and shunt switch element. This method includes closing the series switch element during a first period, the series switch element comprising a plurality of series switch elements segments. The method includes applying a switching gate voltage to gates of series switching transistors of a subset of the plurality of series switch elements segments of the series switch element, wherein only the series switching transistors of the subset of the plurality of series switch elements segments of the series switch element turn on, while series protection transistor of more than the subset of the plurality of series switch elements segments of the series switch element turn on. The shunt switch element during is closed during a second period.

Abstract: Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One method includes generating, by a switching controller, a switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and generating an output voltage by filtering the switching voltage with an output inductor and a load capacitor. The method further includes generating an assisting current based on a value of current conducted through the output inductor, and assisting the load current by summing the assisting current with the current conducted through the inductor.

Abstract: Embodiments of systems, methods and apparatuses of a switching voltage regulator are disclosed. One switching voltage regulator includes a series switch element, a shunt switch element, a PWM controller, and a mode controller. The PWM controller includes an error amplifier and a switching controller. The error amplifier generates an error signal based on a difference between a reference voltage and an output voltage. Further, the switching controller is operative to generate switch element control voltages based on the error signal, for controlling opening and closing of the series switch element and the shunt switch element, wherein the opening and closing of the series switch element and the shunt switch element generates a switching voltage. The mode controller is operative adjust a gain of the error amplifier over a selected range of frequencies based on a parameter indicative of a likelihood of oscillations in the output voltage.

Abstract: Methods, apparatuses and systems for assisting an output current of a voltage converter, are disclosed. One method includes detecting a request for a positive change in an output voltage of the voltage converter, selecting an output current assist value based on the requested positive change in the output voltage, for a predetermined load, and assisting the output current with the selected output assist current.

Abstract: Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One apparatus includes a switching voltage regulator, wherein the switching voltage regulator includes a series switch element, a shunt switch element, a switching controller and a switched output filter. The switching controller is configured to generate a switching voltage through controlled closing and opening of the series switch element and the shunt switch element. The switched output filter filters the switching voltage and generates a regulated output voltage, wherein the switched output filter includes a plurality of capacitors that are selectively included within the switched output filter.

Abstract: Embodiments of systems, methods and apparatuses of a voltage regulator are disclosed. One apparatus of the voltage regulator includes a series switch element, wherein the series switch element comprises a plurality of partitioned series switch elements, a shunt switch element, and a switching controller. The switching controller is operative to control the series switch element and the shunt switch element in an idle state, wherein none of the plurality of partitioned series switch elements are active, control the series switch element and the shunt switch element in a burst state, wherein N of the plurality of partitioned series switch elements are active, and control the series switch element and the shunt switch element in a transition state, wherein M of the plurality of partitioned series switch elements are active, and wherein M is less than N.

Abstract: Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One method includes generating, by a switching controller, a switching voltage through controlled closing and opening of a series switch element and a shunt switch element. Further, the method includes generating, by a switchable output filter, a regulated output voltage by filtering the switching voltage, wherein the switchable output filter comprises a plurality of capacitors that are selectively included within the switchable output filter.

Abstract: Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.

Abstract: Embodiments of systems, methods and apparatuses of a switching voltage regulator are disclosed. One switching voltage regulator includes a series switch element, a shunt switch element, a PWM controller, and a mode controller. The PWM controller includes an error amplifier and a switching controller. The error amplifier generates an error signal based on a difference between a reference voltage and an output voltage. Further, the switching controller is operative to generate switch element control voltages based on the error signal, for controlling opening and closing of the series switch element and the shunt switch element, wherein the opening and closing of the series switch element and the shunt switch element generates a switching voltage. The mode controller is operative adjust a gain of the error amplifier over a selected range of frequencies based on a parameter indicative of a likelihood of oscillations in the output voltage.

Abstract: Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One method includes generating, by a switching controller, a switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and generating an output voltage by filtering the switching voltage with an output inductor and a load capacitor. The method further includes generating an assisting current based on a value of current conducted through the output inductor, and assisting the load current by summing the assisting current with the current conducted through the inductor.

Abstract: Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One apparatus includes a switching voltage regulator, wherein the switching voltage regulator includes a series switch element, a shunt switch element, a switching controller and a switched output filter. The switching controller is configured to generate a switching voltage through controlled closing and opening of the series switch element and the shunt switch element. The switched output filter filters the switching voltage and generates a regulated output voltage, wherein the switched output filter includes a plurality of capacitors that are selectively included within the switched output filter.