Abstract: An information transmission unit includes a signal source, a channel having a channel cutoff frequency coupled to the signal source, a continuous-time linear active filter coupled to the channel to provide equalization over a range of frequencies, and a sampling unit coupled to the continuous-time linear active filter. A method includes transmitting a continuous time signal including digital information on a channel, receiving the continuous time signal from the channel and filtering the continuous time signal to form an equalized continuous time signal, and sampling the equalized continuous time signal to recover the digital information.

Abstract: A variable offset amplifier circuit includes two differential transistor pairs and a variable current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor. The first transistors are matched in size, as are the second transistors. The bias terminals of the first and second transistors serve as inputs to the amplifier circuit. The output of the amplifier circuit is associated with the differential pair output nodes of only similarly sized transistors, such that loads at the output of the amplifier circuit are sourced with current only from similarly sized transistors of the transistor pairs. The variable current generators may be adjusted to create offset in the output of amplifier circuit. The amplifier circuit has applications in a comparator circuit that also has a regenerative latch circuit, and as a sense amplifier in a receiver of a communications system.

Abstract: According to some embodiments, a circuit provides a first set of one or more flip-flops to receive a low-swing differential clock, and a second set of one or more flip-flops to receive the low-swing differential clock. One of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.

Abstract: An amplifier includes a differential unit including an input port to receive a voltage input signal, a current mirror unit including an output port, and a voltage-to-current conversion unit to couple the differential unit to the current mirror unit and to generate a current signal to drive the current mirror unit to generate a current output signal at the output port. A method includes receiving a voltage input signal at an input port of a differential unit, converting the voltage input signal to a current signal, and driving a current mirror with the current signal to generate an current output signal at an output port.

Abstract: An electrostatic discharge protection unit includes a channel, a passive filter, and an electrostatic discharge protection circuit. The passive filter and the electrostatic discharge protection circuit are formed on a substrate. The electrostatic discharge protection circuit couples the channel to the passive filter. A method includes, for a channel having a bandwidth determining the bandwidth, and generating a transfer function for a passive filter which when combined in series an electrostatic discharge protection circuit and the channel yields a combination transfer function which has a combination bandwidth that is greater than the channel transfer function bandwidth.

Abstract: According to some embodiments, a circuit is adapted to convert a first voltage signal from a bidirectional signal line to a first current signal, the first voltage signal to represent first data transmitted from a first transmitter and second data transmitted from a second transmitter. The circuit may be further operable to convert a second voltage signal to a second current signal, the second voltage signal, substantially to represent the first data, and to generate a first output signal to represent the second data based on the second current signal and the first current signal. Such a circuit might be an element of a simultaneous bidirectional signaling transceiver.

Abstract: According to some embodiments, a device includes a phase generator to generate m control signals, each of the m control signals associated with a respective signal period, and at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a signal sample according to a signal period associated with the received control signal, and to modulate the signal sample according to a weighting coefficient associated with the tap. The device further includes m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters and to output a sum of signal samples modulated by the taps of the associated filter in response to one of the m control signals associated with a signal period other than the signal periods according to which the signal samples were acquired.

Abstract: According to some embodiments, a circuit includes a current mirror to receive a multi-level current signal, and to generate a plurality of current signals substantially identical to the multi-level current signal. Such a circuit may also include a plurality of current comparison circuits, each of the plurality of current comparison circuits to receive a respective one of the plurality of generated current signals, to receive a respective reference current signal, and to generate a signal indicating a relationship between the received respective one of the plurality of generated current signals and the respective reference current signal.

Abstract: An amplifier includes a differential pair including a pair of input ports and a pair of output ports and a nonlinear load coupled to the differential pair. The pair of output ports is coupled to the pair of input ports to provide negative feedback. The pair of output ports is coupled to the non-linear load to provide positive feedback. A method includes receiving a signal at an input port of an amplifier and processing the signal in the amplifier by coupling negative feedback and positive feedback produced in the amplifier by the signal to the input port.

Abstract: According to some embodiments, a circuit provides a first set of one or more flip-flops to receive a low-swing differential clock, and a second set of one or more flip-flops to receive the low-swing differential clock. One of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.

Abstract: A current reference with reduced sensitivity to process variations includes a variable resistor and a control transistor. The control transistor has a current from source-to-drain that is provided by a current mirror. The current mirror also provides a current to a variable resistor that is coupled gate-to-source to the control transistor. A control loop circuit measures the reference current provided by the current mirror and modifies the resistance value of the variable resistor in response. An external precision resistor is used to measure the reference current, and current variations as a result of process variations are reduced.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: A high gain amplifier circuit includes two differential transistor pairs and a current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor and an output node for each. Bias terminals of the first transistors serve as inputs for the amplifier circuit. The output node of each first transistor serves as an output for the amplifier circuit and is respectively coupled to the bias terminal of the second transistor of the same differential pair. The amplifier circuit has applications in a comparator circuit that also has a load circuit, which may have active components or only passive components. The amplifier circuit may also be used as a sense amplifier in a receiver of a communications system.

Abstract: First and second differential transistor pairs, where each may be intentionally unbalanced or balanced, are provided. First and second digitally variable current generators are coupled to control respective tail currents of the first and second differential pairs. A switch circuit may be coupled to equalize the voltages of the respective tail current nodes. A common mode feedback circuit is also described, to improve common mode rejection of the overall amplifier. Applications of the amplifier circuit include sense amplifiers and comparators.

Abstract: According to some embodiments, a circuit includes two voltage dividers, each adapted to receive different ones of two signals, the two signals together representing a data signal, and a comparator to compare a voltage generated by a first of the two voltage dividers with a voltage generated by a second of the two voltage dividers.

Abstract: An optical receiver includes a photodiode, a variable current source, and a current mode comparator.

Abstract: An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active cascode differential latch has a relatively small input impedance, and has utility for comparators and discrete-time analog filters, to name just a few, particularly when used in high bandwidth and low voltage applications.

Abstract: A high gain amplifier circuit includes two differential transistor pairs and a current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor and an output node for each. Bias terminals of the first transistors serve as inputs for the amplifier circuit. The output node of each first transistor serves as an output for the amplifier circuit and is respectively coupled to the bias terminal of the second transistor of the same differential pair. The amplifier circuit has applications in a comparator circuit that also has a load circuit, which may have active components or only passive components. The amplifier circuit may also be used as a sense amplifier in a receiver of a communications system.

Abstract: A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions.