Abstract: A current mirror includes an input node to receive an input current, an output node to produce an output current, and a reference node. The current mirror also includes a potential reduction unit to allow the voltage at the input node to be less than the voltage at the reference node.

Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.

Abstract: A current mirror includes an input node to receive an input current, an output node to produce an output current, and a reference node. The current mirror also includes a potential reduction unit to allow the voltage at the input node to be less than the voltage at the reference node.

Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: A high gain amplifier circuit includes two differential transistor pairs and a current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor and an output node for each. Bias terminals of the first transistors serve as inputs for the amplifier circuit. The output node of each first transistor serves as an output for the amplifier circuit and is respectively coupled to the bias terminal of the second transistor of the same differential pair. The amplifier circuit has applications in a comparator circuit that also has a load circuit, which may have active components or only passive components. The amplifier circuit may also be used as a sense amplifier in a receiver of a communications system.

Abstract: A variable offset amplifier circuit includes two differential transistor pairs and a variable current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor. The first transistors are matched in size, as are the second transistors. The bias terminals of the first and second transistors serve as inputs to the amplifier circuit. The output of the amplifier circuit is associated with the differential pair output nodes of only similarly sized transistors, such that loads at the output of the amplifier circuit are sourced with current only from similarly sized transistors of the transistor pairs. The variable current generators may be adjusted to create offset in the output of amplifier circuit. The amplifier circuit has applications in a comparator circuit that also has a regenerative latch circuit, and as a sense amplifier in a receiver of a communications system.

Abstract: A high gain amplifier circuit includes two differential transistor pairs and a current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor and an output node for each. Bias terminals of the first transistors serve as inputs for the amplifier circuit. The output node of each first transistor serves as an output for the amplifier circuit and is respectively coupled to the bias terminal of the second transistor of the same differential pair. The amplifier circuit has applications in a comparator circuit that also has a load circuit, which may have active components or only passive components. The amplifier circuit may also be used as a sense amplifier in a receiver of a communications system.

Abstract: A circuit samples a voltage on a simultaneous bi-directional bus, and subtracts an outbound voltage to determine an inbound voltage. Sampling capacitors are variable to adjust for matching time constants. A mechanism is provided to sample error voltages over clock phase variations and sampling capacitor values.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter and a current multiplier in a single stage so as to provide a current signal indicative of a weighted sampled voltage signal. The current signals are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential.

Abstract: First and second differential transistor pairs, where each may be intentionally unbalanced or balanced, are provided. First and second variable current generators are coupled to control respective tail currents of the first and second differential pairs. A switch circuit is coupled to equalize the voltages of the respective tail current nodes. Applications of the amplifier circuit include sense amplifiers and comparators.

Abstract: A differential amplifier includes a source coupled differential pair of transistors. A feedback loop detects the presence of an input referred offset in the differential amplifier and modifies a body bias voltage on at least one of the transistors in the differential pair. A comparator detects a differential output voltage when the differential input voltage is set to zero. In some embodiments, a charge pump in the feedback loop injects charge on the body of the transistor to modify the bias voltage. In other embodiments, a digital-to-analog converter receives a digital control word and produces a bias voltage on the body of the transistor.

Abstract: A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

Abstract: A differential amplifier includes a source coupled differential pair of transistors. A feedback loop detects the presence of an input referred offset in the differential amplifier and modifies a body bias voltage on at least one of the transistors in the differential pair. A comparator detects a differential output voltage when the differential input voltage is set to zero. In some embodiments, a charge pump in the feedback loop injects charge on the body of the transistor to modify the bias voltage. In other embodiments, a digital-to-analog converter receives a digital control word and produces a bias voltage on the body of the transistor.

Abstract: First and second differential transistor pairs, where each may be intentionally unbalanced or balanced, are provided. First and second variable current generators are coupled to control respective tail currents of the first and second differential pairs. A switch circuit is coupled to equalize the voltages of the respective tail current nodes. Applications of the amplifier circuit include sense amplifiers and comparators.

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.

Abstract: A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

Abstract: A current reference with reduced sensitivity to process variations includes a variable resistor and a control transistor. The control transistor has a current from source-to-drain that is provided by a current mirror. The current mirror also provides a current to a variable resistor that is coupled gate-to-source to the control transistor. A control loop circuit measures the reference current provided by the current mirror and modifies the resistance value of the variable resistor in response. An external precision resistor is used to measure the reference current, and current variations as a result of process variations are reduced.

Abstract: A variable offset amplifier circuit includes two differential transistor pairs and a variable current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor. The first transistors are for coupling to first and second loads. A current mirror and shunt is coupled to shunt a portion of current flowing through one of the first transistors from flowing through a correspondingly coupled load. The shunt current is mirrored from one of the second transistors to provide either positive current feedback or negative current feedback. The amplifier circuit has applications in a comparator circuit that also has a regenerative latch circuit, and as a sense amplifier in a receiver of a communications system.