Patents by Inventor James E. Miller, Jr.
James E. Miller, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8281193Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. A signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: December 13, 2011Date of Patent: October 2, 2012Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Publication number: 20120084612Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. A signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: ApplicationFiled: December 13, 2011Publication date: April 5, 2012Applicant: MICRON TECHNOLOGY, INC.Inventor: James E. Miller, JR.
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Patent number: 8086920Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. A signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: May 19, 2008Date of Patent: December 27, 2011Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 7376874Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: March 19, 2004Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6760875Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: May 30, 2003Date of Patent: July 6, 2004Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6591386Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: May 22, 2002Date of Patent: July 8, 2003Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6421800Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: September 8, 2000Date of Patent: July 16, 2002Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6392458Abstract: The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.Type: GrantFiled: December 7, 1999Date of Patent: May 21, 2002Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld
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Patent number: 6359482Abstract: A method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.Type: GrantFiled: August 30, 2000Date of Patent: March 19, 2002Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld
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Patent number: 6316976Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.Type: GrantFiled: April 28, 2000Date of Patent: November 13, 2001Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld, Manny Ma, R. Jacob Baker
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Patent number: 6300668Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.Type: GrantFiled: August 17, 1999Date of Patent: October 9, 2001Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Manny K. F. Ma
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Patent number: 6289479Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: September 8, 2000Date of Patent: September 11, 2001Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6281726Abstract: An inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor.Type: GrantFiled: March 15, 2000Date of Patent: August 28, 2001Assignee: Micron Technolgy, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6137325Abstract: An inventive digital delay locked loop (DLL) for outputting at least first and second output clocks includes delay elements for receiving an input clock and outputting a first series of delayed clocks, each lagging the input clock more than its predecessor. A phase detector compares relative phases of the first output clock and the input clock and outputs count-up or count-down control signals in accordance therewith. First and second counters output respective first and second counts in response to the count-up or count-down control signals, and a first multiplexer selects and outputs the first output clock from among the first series of delayed clocks in accordance with the first count. Also, interpolation circuitry receives a portion of the first series of delayed clocks and outputs same, along with a plurality of interpolated clocks, in the form of a second series of delayed clocks, each lagging the input clock more than its predecessor.Type: GrantFiled: June 22, 1998Date of Patent: October 24, 2000Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6137334Abstract: The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.Type: GrantFiled: July 6, 1998Date of Patent: October 24, 2000Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld
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Patent number: 6138258Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: June 3, 1999Date of Patent: October 24, 2000Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 6069506Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.Type: GrantFiled: May 20, 1998Date of Patent: May 30, 2000Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld, Manny Ma, R. Jacob Baker
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Patent number: 5990538Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.Type: GrantFiled: November 3, 1997Date of Patent: November 23, 1999Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Manny K. F. Ma
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Patent number: 5944845Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.Type: GrantFiled: June 26, 1997Date of Patent: August 31, 1999Assignee: Micron Technology, Inc.Inventor: James E. Miller, Jr.
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Patent number: 5936974Abstract: A selector circuit (12) for placing a memory device (10) in test mode. The selector circuit (12) uses a logic circuit (26) to determine when a control signal provided to a pin of the memory device (10) maintains a first logic level for a period of time exceeding the specification for the control signal in normal operation. A multiplexer (24) receives the control signal and a substitute control signal at an alternate pin of the memory device. The substitute control signal is used in place of the control signal during the test. The output of the logic circuit (26) is coupled to control the multiplexer (24) to select the control signal for use in addressing a cell of the memory device (10) in normal operation and to select the substitute control signal for use in addressing a cell of the memory device (10) in test mode.Type: GrantFiled: August 22, 1997Date of Patent: August 10, 1999Assignee: Micron Technology, Inc.Inventors: Gordon Roberts, James E. Miller, Jr., Eric Stubbs