Abstract: The present disclosure relates to novel compounds for use in therapeutic treatment of a disease associated with peptidylarginine deiminases (PADs), such as peptidylarginine deiminase type 4 (PAD4). The present disclosure also relates to processes and intermediates for the preparation of such compounds, methods of using such compounds and pharmaceutical compositions comprising the compounds described herein.

Abstract: Formation of methanoic acid, during the production of Hexahydro-1,3,5-trinitro-1,3,5-triazine and Octahydro-1,3,5,7-tetranitro-1,3,5,7-tetrazocine via the legacy Bachmann nitrolysis process, is avoided when the workup is performed under neutralized, anhydrous conditions. The recovered anhydrous spent acid is used directly in successive nitrolysis batches with minimal processing. The yield and quality of the hexahydro-1,3,5-trinitro-1,3,5-triazine and octahydro-1,3,5,7-tetranitro-1,3,5,7-tetrazocine thus produced is equal to the yield and quality of the legacy process hexahydro-1,3,5-trinitro-1,3,5-triazine and octahydro-1,3,5,7-tetranitro-1,3,5,7-tetrazocine employing aqueous workup conditions.

Abstract: A slide carrier includes: a base support; and a slide platform having a surface that is parallel to a first plane defined by a first vector and a second vector, wherein a vector extending in a direction opposite to the direction of gravity is normal with respect to a second plane defined by a third vector and a fourth vector, an angle between the first vector and the third vector is greater than zero degrees and less than 90 degrees, and an angle between the second vector and the fourth vector is greater than zero degrees and less than 90 degrees.

Abstract: An aerosol delivery device having a detachable power source is provided. A control body may be coupleable with a cartridge to form an aerosol delivery device. The cartridge may contain an aerosol precursor composition and be equipped with a heating element configured to activate and vaporize components of the aerosol precursor composition. The control body may comprise a housing and a power source detachably coupled to an outer surface of the housing. A control component may be contained within the housing and configured to operate in an active mode in which the control body is coupled with the cartridge. The control component in the active mode may be configured to direct power from the power source to the heating element to activate and vaporize components of the aerosol precursor composition.

Abstract: A slide carrier includes: a base support; and a slide platform having a surface that is parallel to a first plane defined by a first vector and a second vector, wherein a vector extending in a direction opposite to the direction of gravity is normal with respect to a second plane defined by a third vector and a fourth vector, an angle between the first vector and the third vector is greater than zero degrees and less than 90 degrees, and an angle between the second vector and the fourth vector is greater than zero degrees and less than 90 degrees.

Abstract: The present disclosure is directed to specimen processing assemblies including (a) a lower plate (10), (b) an upper plate (30) complementary to the lower plate, and (c) a chamber formed therefrom. In some embodiments, the formed chamber is adapted to perform an unmasking operation, e.g. antigen retrieval and/or target retrieval. In some embodiments, the specimen processing assemblies are configured to maintain a specimen-bearing substrate (15) horizontal during all processing steps. The present disclosure is also directed to systems including one or more independently operable specimen processing assemblies.

Abstract: A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.

Abstract: An example disclosed method includes querying, via a logic circuit, a media processing device memory for files that can be stored to a USB storage device, the USB storage device being connected to a USB Host port of the media processing device; receiving a selection of one of the files to be stored to the USB storage device; determining, via the logic circuit, if the selected one of the files is a particular type of file, and if the selected one of the files is the particular type of file, converting the selected one of the files from a first representation to a second representation; and storing the selected one of the files in the second representation to the USB storage device.

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract: A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract: Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Abstract: Processes and systems for recovering promoter-containing compounds, for example, perrhenates, from promoter-containing catalyst substrates, for example, substrates containing precious metals, such as silver, are disclosed. The processes include contacting the substrates with a first solution adapted to remove at least some of the catalyst promoter from the substrates, for example, an oxidizing agent, to produce a second solution containing catalyst promoter, passing the second solution through a porous medium adapted to capture at least some of the catalyst promoter, for example, a ion exchange resin; and passing a third solution, for example, a base solution, through the porous medium to remove at least some of the catalyst promoter from the porous medium and produce a fourth solution containing compounds having a catalyst promoter. Systems adapted to practice these processes are also disclosed.

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract: Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.

Abstract: Processes and systems for recovering promoter-containing compounds, for example, perrhenates, from promoter-containing catalyst substrates, for example, substrates containing precious metals, such as silver, are disclosed. The processes include contacting the substrates with a first solution adapted to remove at least some of the catalyst promoter from the substrates, for example, an oxidizing agent, to produce a second solution containing catalyst promoter, passing the second solution through a porous medium adapted to capture at least some of the catalyst promoter, for example, a ion exchange resin; and passing a third solution, for example, a base solution, through the porous medium to remove at least some of the catalyst promoter from the porous medium and produce a fourth solution containing compounds having a catalyst promoter. Systems adapted to practice these processes are also disclosed.

Abstract: Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.