Abstract: The present invention provides a method for purifying ruthenium sources to obtain high purity ruthenium metal and form a ruthenium metal pattern on a semiconductor substrate without the need for high temperature processing or a complex series of wet processes. A gas stream including ozone (O3) is brought into contact with a ruthenium source in one or more reaction vessels to form ruthenium tetraoxide (RuO4), a compound that is a gas at the reaction conditions. The ruthenium tetraoxide, along with unreacted ozone and the remainder of the gas stream is then fed into a collection vessel where the gaseous ruthenium tetraoxide is reduced to form a ruthenium dioxide (RuO2) layer on a semiconductor substrate. The deposited ruthenium dioxide is then reduced, preferably with hydrogen, to produce highly pure ruthenium metal that may be, in turn, patterned and dry etched using ozone as an etchant gas.

Abstract: The present invention relates to an apparatus for obtaining high purity ruthenium metal without the need for high temperature processing, expensive reagents, complex series of wet processes, or expensive equipment. According to the present invention, a gas stream including ozone (O3) is brought into contact with a ruthenium source in one or more reaction vessels. The ozone reacts with the ruthenium source to form ruthenium tetraoxide (RuO4), a compound that is a gas at the reaction conditions. The ruthenium tetraoxide, along with unreacted ozone and the remainder of the gas stream is then fed into a collection vessel where a major portion of the m gaseous ruthenium tetraoxide is thermally reduced to form ruthenium dioxide (RuO2) deposits within the collection vessel. The deposited ruthenium dioxide is then reduced to produce highly pure ruthenium metal.

Abstract: The present invention provides a method for purifying ruthenium sources to obtain high purity ruthenium metal without the need for high temperature processing, expensive reagents, complex series of wet processes, or expensive equipment. According to the present invention, a gas stream including ozone (O3) is brought into contact with a ruthenium source, such as a commercial ruthenium metal sponge, in one or more reaction vessels. The ozone reacts with the ruthenium present in the ruthenium source to form ruthenium tetraoxide (RuO4), a compound that is a gas at the reaction conditions. The ruthenium tetraoxide, along with unreacted ozone and the remainder of the gas stream is then fed into a collection vessel where a major portion of the gaseous ruthenium tetraoxide is thermally reduced to form ruthenium dioxide (RuO2) deposits within the collection vessel.

Abstract: Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple functional units from which the appropriate status must be selected for controlling the sequencing of microinstructions. This is especially true in horizontally microcoded machines. The adverse affects on the delay can be reduced by using a staged multiplexor design. For the staged multiplexor to be useful, all functional unit status should be produced as early as possible. In this invention, a status predictor is described that allows the status associated with the shifter to be generated directly from the inputs to the shifter.

Abstract: A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM.

Abstract: An apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction. The apparatus is applicable to all Enterprise Systems Architecture (ESA)/390 addressing modes encompassing access register addressing for either 24 bit or 31 bit addressing. S/370 addressing in 24 bit and 31 bit modes are also supported by the proposed apparatus and treated as special cases of access register addressing. In addition, the apparatus is extended to support other addressing modes with an example provided to include a 64 bit addressing mode. A fast parallel implementation of the apparatus is also presented. The apparatus results in a one cycle savings for all invocations of the MVC instruction which comprises approximately 2% of the dynamic instruction stream of a representative instruction mix.

Abstract: In a digital computer system both rotation of bits in a data byte and rotation in combination with additional manipulation, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the sequence of input bits are maintained on the output bit lines when the bits on the input lines are considered as arranged in a circle, and in a non-cyclic mode of operation, connects the input bit lines to the output bit lines in a manner to execute gather operations and spread operations.

Abstract: A high speed three-to-one data dependency collapsing ALU can be used to support multiple issue of instructions. The computing apparatus supports multiple issue of instructions it is useful in CISC, superscalar, superscalar RISC, etc. type computer designs. The concept of the ALU is presented along with a detailed description of a design. The apparatus allows the execution of any combination of two independent or dependent arithmetic or logical instructions in a single machine cycle. The 3-1 collapsing ALU structure has a 3-2 carry save adder (CSA); and a 2-1 control arithmetic logic unit (CALU) coupled for an input from the carry save adder; and a first pre-adder logic block coupled with an output to the control arithmentic logic unit; and a control generator; and a second controlled logic block coupled to receive an input from said control generator and having its output coupled to said control arithmetic logic unit.

Abstract: An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic instruction pairs is developed. The algorithm is then applied to three interlock collapsing ALU means implementations that have been proposed. The critical path for calculating the carries is first presented. Next the expression for generating these carries is used to derive a fast implementation for generating overflow which is implemented in the apparatus.

Abstract: An apparatus for the reduction of partial products of a multiplier combines attributes of pre-addition and the regularity found in array multipliers by employing improved four-to-two composite counter cells. This composite counter cell, the basic block for reducing the partial products, is itself comprised of two new four-to-two counters. One of the four-to-two counters is used to perform pre-addition of the partial products while the second counter is used to perform addition between the sum produced by the counter performing the pre-addition and the outputs from the second counter of a cell in a previous stage of the addition. The regularity of array multiplication schemes is preserved and interconnections required by the mechanism span no more than two columns of the matrix.

Abstract: A mechanism is presented for detecting overflow in an interlock collapsing hardware apparatus that simultaneously executes two instructions. The overflow is determined as if the second instruction executes by itself using results from execution of the first instruction. Overflow detection is accomplished by using only values input into, and generated within, the interlock collapsing apparatus.

Abstract: Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of the implementations the delay is shown to be an equivalent number of stages as required by a three-to-one adder assuming a commonly available bookset. The delay for the other two implementations is comparable to the three-to-one adder. In addition, trade-offs for the design complexity of implementation alternatives are set out. The embodiments achieve minimum delays without a prohibitive increase in hardware.

Abstract: A molecular spectrometer is provided that performs Fourier analysis utilizing the discrete Fourier Transform on a digitized time domain waveform that relates to the composition of a sample. Digitized reference waveforms are employed to permit the instrument to limit its analysis to frequencies of interest and thereby increase the rapidity of the analysis. Data at differing frequencies can be resolved at independent resolutions, and the instrument can analyze spectroscopic data in real time.

Abstract: A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.

Abstract: Thin film photovoltaic cells having a pair of semiconductor layers between an opaque and a transparent electrical contact are manufactured in a method which includes the step of scanning one of the semiconductor layers to determine the location of any possible shorting defect. Upon the detection of such defect, the defect is eliminated to increase the durability and yield of the photovoltaic device.

Abstract: Apparatus is disclosed for attaching a flexible annular member to a rigid member using an annular tongue on an annular bead on one of the members that is engageable in an annular groove in an annular bead on the other member, and further using a preformed resilient lock ring that is split so as to have oppositely facing ends and has a C-shaped cross-section with a radially outwardly facing peripheral side so as to be mountable over and then clamp together and hold the beads on the members with their tongue and groove engaged.

Abstract: A paper dispensing apparatus includes a platform having a pair of wheels and a housing attached to the platform. A plurality of shafts extend upward from the platform to respectively support different widths of paper rolls. A handle may be attached to the housing to assist manipulation of the apparatus by an operator. Cutting blades are mounted in the housing adjacent the respective paper rolls and operate through vertical movement by means of a drawn cable. A shaft extends upward from the platform to support masking tape rolls at a position to overlap the side edge of the paper rolls. Adjustable retaining collars are provided to accommodate varying widths of paper rolls. Retaining springs are provided to apply tension to the paper rolls.

Abstract: A device for converting a conventional combine into a unit which will crush and recover corn cobs as well as recover shelled corn comprising a flat perforated metal element which will replace the conventional chaffer and sieve in the final cleaning mechanism of the combine, the element having a plurality of fins protruding above the upper surface thereof adapted to channel and direct the flow of corn stocks and chaff thereover, the holes being of a size sufficient to allow the passage of corn cob particles therethrough.

Abstract: A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.