Patents by Inventor James Fred Salzman
James Fred Salzman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170062377Abstract: A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.Type: ApplicationFiled: August 28, 2016Publication date: March 2, 2017Applicant: Texas Instruments IncorporatedInventor: James Fred Salzman
-
Publication number: 20160190237Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: James Fred Salzman, Charles Clayton Hadsell
-
Publication number: 20160163794Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.Type: ApplicationFiled: January 28, 2016Publication date: June 9, 2016Inventor: James Fred Salzman
-
Publication number: 20160141389Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.Type: ApplicationFiled: January 28, 2016Publication date: May 19, 2016Inventor: James Fred Salzman
-
Patent number: 9281245Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.Type: GrantFiled: December 10, 2013Date of Patent: March 8, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: James Fred Salzman, Charles Clayton Hadsell
-
Patent number: 9281232Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.Type: GrantFiled: September 25, 2014Date of Patent: March 8, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: James Fred Salzman
-
Patent number: 9079002Abstract: A method of forming a drug delivery device includes laser forming a top ceramic plate to include an inner portion including top laser micromachined through-holes while not lasering a planar outer portion. Top nanochannels are formed into the top ceramic plate to provide fluid connections between neighboring to micromachined through-holes. A bottom ceramic plate is laser formed to include an inner portion including bottom laser micromachined through-holes while not lasering a planar outer portion. Bottom nanochannels are formed into the bottom ceramic plate to provide fluid connections between neighboring to micromachined through-holes. A bonding material is applied to the planar outer portion of the top and/or bottom ceramic plate. The top and bottom ceramic plate are aligned so that the top and bottom laser micromachined through-holes are laterally offset from one another. The top ceramic plate is bonded to the bottom ceramic plate with a bonding material.Type: GrantFiled: February 7, 2014Date of Patent: July 14, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: James Fred Salzman
-
Publication number: 20150108588Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.Type: ApplicationFiled: September 25, 2014Publication date: April 23, 2015Inventor: James Fred Salzman
-
Patent number: 9006864Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.Type: GrantFiled: November 6, 2013Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: James Fred Salzman, Richard Guerra Roybal, Randolph William Kahn
-
Publication number: 20140183707Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.Type: ApplicationFiled: December 10, 2013Publication date: July 3, 2014Inventors: James Fred SALZMAN, Charles Clayton HADSELL
-
Publication number: 20140124895Abstract: A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an intrinsic p-type base region of the NPN bipolar junction transistor at a boundary of the intrinsic p-type base region with a dielectric layer over a substrate of the semiconductor device, between an emitter of the NPN bipolar junction transistor and an extrinsic p-type base region of the NPN bipolar junction transistor. The p-type RIDS region has a doping density high enough to prevent inversion of a surface of the p-type RIDS region adjacent to the dielectric layer when trapped charge is accumulated in the dielectric layer, while the intrinsic p-type base region may invert from the trapped charge forming the radiation induced diode structure. The p-type RIDS region is separated from the emitter and from the extrinsic base region by portions of the intrinsic base region.Type: ApplicationFiled: November 6, 2013Publication date: May 8, 2014Applicant: Texas Instruments IncorporatedInventors: James Fred SALZMAN, Richard Guerra ROYBAL, Randolph William KAHN
-
Patent number: 8530298Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.Type: GrantFiled: November 1, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventors: Richard G. Roybal, Shariq Arshad, Shaoping Tang, James Fred Salzman
-
Publication number: 20130126508Abstract: A method of increasing the operating life of a semiconductor device that is to be used in a harsh ionizing radiation environment including determining heating criteria for annealing the device; installing the device in an electronic apparatus; and heating the installed device with a local heating source in accordance with the heating criteria.Type: ApplicationFiled: December 1, 2011Publication date: May 23, 2013Applicant: Texas Instruments IncorporatedInventors: James Fred Salzman, Charles Clayton Hadsell
-
Publication number: 20130105904Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: RICHARD G. ROYBAL, SHARIQ ARSHAD, SHAOPING TANG, JAMES FRED SALZMAN
-
Patent number: 7453142Abstract: A transformer system includes a package substrate having a surface. A plurality of electrically conductive pads are arranged in spaced apart relationship relative to each other on the substrate surface. A first winding is defined by a first electrically conductive path between a first input and a first output, the first electrically conductive path including at least one wire connected between at least one first pad pair of the electrically conductive pads. At least one electrically conductive pad of each first pad pair is at the substrate surface. A second winding is defined by a second electrically conductive path between a second input and a second output, the second electrically conductive path including at least one wire connected between at least one second pad pair of the electrically conductive pads. At least one electrically conductive pad of each second pad pair is at the substrate surface.Type: GrantFiled: December 5, 2005Date of Patent: November 18, 2008Assignee: Texas Instruments IncorporatedInventors: See Taur Lee, Solti Peng, Dirk Leipold, James Fred Salzman
-
Publication number: 20080084311Abstract: In a described implementation of inductance enhancement by magnetic material introduction, a substrate that supports an inductive element has magnetic material introduced thereto.Type: ApplicationFiled: October 6, 2006Publication date: April 10, 2008Applicant: Texas InstrumentsInventor: James Fred Salzman
-
Publication number: 20080023824Abstract: In a described implementation for double-sided die utilization, a die includes at least one die feature on a first side and at least one die feature on a second side. The die features on the first and second sides are electrically interconnected by way of through vias.Type: ApplicationFiled: July 28, 2006Publication date: January 31, 2008Inventor: James Fred Salzman