Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: An apparatus to test a semiconductive device includes a base plane that holds at least one heat-transfer fluid unit cell. The at least one heat-transfer fluid unit cell includes a fluid supply structure including a supply-orifice cross section as well as a fluid return structure including a return-orifice cross section. The supply-orifice cross section is greater than the return-orifice cross section. A die interface is also included to be a liquid-impermeable material.

Abstract: The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap.

Abstract: A thermal interface material is provided using composite particles. Advantages include increased thermal conductivity and improved mechanical properties such as lower viscosity. In selected embodiments free particles such as metallic particles or carbon nanotubes, etc. are included in a thermal interface material along with composite particles. An advantage of including free particles along with composite particles includes improved packing density within selected embodiments of thermal interface materials.

Abstract: Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A method and arrangement for dissipating heat from a localized area within a semiconductor die is presented. A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area. As such, thermal stress on the die is reduced, and total heat from the die is more readily dissipated.

Abstract: The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap.

Abstract: An electronic device includes a die further having a first major surface, and a second major surface. The electronic device also includes a plurality of connectors associated with the first major surface of the die, and an integrated heat spreader in thermally conductive relation with the second major surface of the die. The integrated heat spreader also has a layer of silicon, and a layer of diamond attached to the layer of silicon. The first major surface of the die attached to a printed circuit board. A method for forming a heat dissipating device includes placing a layer of diamond on a silicon substrate, and thinning the silicon substrate. The substrate is diced to form a plurality of heat dissipating devices sized to form a thermally conductive connection to a die. A surface of the silicon substrate is placed in thermal communication with a source of heat.

Abstract: A method and arrangement for dissipating heat from a localized area within a semiconductor die is presented. A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area. As such, thermal stress on the die is reduced, and total heat from the die is more readily dissipated.

Abstract: A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes.

Abstract: A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Abstract: A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Abstract: A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes.

Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.