Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.

Abstract: A surface wave apparatus is disclosed having reduced sound attenuation across a surface along a known path having a path distance when compared to sound attenuation along a same path distance through air. The surface wave apparatus includes a plurality of cells defining a first surface. Sound presented at the first surface forms a surface wave over the surface and proximate thereto. Each cell includes four bounding walls and a bottom. Two of the bounding walls act to guide the sound within the known path and two are disposed across the known path to form a structure supporting formation of surface waves.

Abstract: A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

Abstract: A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

Abstract: A method and apparatus for reducing the acoustic coupling between a sound receiving transducer and a sound transmitting transducer is disclosed. A housing, wherein the receiving transducer and the transmitting transducer are mounted, is provided to increase the acoustic separation between the receiving transducer and the transmitting transducer. The housing has a surface, which may have an acoustic impedance condition, which is preferably resistive. The housing may further act as a barrier structure between the receiving transducer and the transmitting transducer.

Abstract: A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Abstract: A surface wave apparatus is disclosed having reduced sound attenuation across a surface along a known path having a path distance when compared to sound attenuation along a same path distance through air. The surface wave apparatus includes a plurality of cells defining a first surface. Sound presented at the first surface forms a surface wave over the surface and proximate thereto. Each cell includes four bounding walls and a bottom. Two of the bounding walls act to guide the sound within the known path and two are disposed across the known path to form a structure supporting formation of surface waves.

Abstract: A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for a producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

Abstract: A system for detecting charge accumulation during semiconductor wafer manufacturing including a sensor comprising a capacitor, an emitter for directing a primary electron beam toward the sensor, wherein the primary electron beam causes the sensor to emit secondary electrons and a detector for measuring the secondary electrons.

Abstract: A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Abstract: A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

Abstract: An ESD protective device is formed having a repeatable gap dimension for reliable protection by the formation of a discharge, using the materials of the gate stack for economy and a sacrificial dielectric formed between the plug and the other terminal for repeatable definition of a discharge gap.

Abstract: A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

Abstract: A control cable and conduit assembly mounting system includes a pair of integrally formed, arcuate, spaced-apart, flexible flanges which substantially encircle a hollow handlebar or frame member. Also included is a post contained between the flanges which extends through a hole formed in the wall of the tubular handlebar or frame member. The post provides axial and rotational position stability and resists displacing forces caused by movement of the control cable or other forces tending to move the control cable along or rotate the conduit around the handlebar or frame member. The flexible flanges maintain the control cable and conduit assembly in a position proximate to the handlebar or frame member. The elimination of the use of screws or fasteners allows for the cable center line to be parallel with the center line of the handlebar or frame member.

Abstract: A non-contact in-situ temperature measurement apparatus for a single crystal substrate such as a semiconductor wafer using X-ray diffraction. Utilizing the Bragg condition for X-ray diffraction, the lattice constant of the semiconductor substrate can be determined either by measuring the diffraction angle for a monochromatic X-ray (monochromatic approach) or by measuring the wavelength of an X-ray diffracted with a certain scattering angle (polychromatic approach). The lattice constant, as a well-known function of temperature, is finally converted into the temperature of the semiconductor substrate.

Abstract: The invention is directed to a semi-conductor wafer processing machine including an arm having a wafer carrier disposed at one end. The wafer carrier is rotatable with the rotating motion imparted to a semi-conductor wafer held thereon. In first embodiment, the machine further includes a rotatable polishing pad having an upper surface divided into a plurality of wedge-shaped sections, including an abrasion section and a polishing section. The abrasion section has a relatively rough texture and the polishing section has a relatively fine texture as compared to each other. In an alternative embodiment, the pad includes an underlayer and surface layer. The surface layer includes two sections of differing hardness, both of which are harder than the underlayer. Alternatively, the surface layer may include one relatively hard section, and the underlayer may include two sections, one of which has the same hardness as the surface layer and the other of which is softer than the surface layer.

Abstract: An improved etch behavior is promoted to generate vertical sidewalls for fuse links that will promote reliable and repeatable laser cutting of the fuse links. In one embodiment, dummy structures are added adjacent to fuse links in order to obtain the vertical sidewalls for reliable fuse deletion. The dummy structures form no part of the fuse or circuit structure but, because of the proximity of the dummy structures to the fuse links, vertical sidewalls are promoted in a reactive ion etch which is used to form the fuse array. In another embodiment, the vertical sidewalls of the fuse links are achieved in a damascene process in which grooves are formed in an oxide layer and filled with a metal. These grooves correspond to the fuse links and alternating dummy structures. Once filled, the surface is planarized using a chemical-mechanical process. The dummy structures provide reinforcement for the metallization (metal and dielectric film), maintaining the integrity of the metallization.

Abstract: Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element.

Abstract: The invention is directed to a semi-conductor wafer processing machine including an arm having a wafer carrier disposed at one end. The wafer carrier is rotatable with the rotating motion imparted to a semi-conductor wafer held thereon. In first embodiment, the machine further includes a rotatable polishing pad having an upper surface divided into a plurality of wedge-shaped sections, including an abrasion section and a polishing section. The abrasion section has a relatively rough texture and the polishing section has a relatively fine texture as compared to each other. In an alternative embodiment, the pad includes an underlayer and surface layer. The surface layer includes two sections of differing hardness, both of which are harder than the underlayer. Alternatively, the surface layer may include one relatively hard section, and the underlayer may include two sections, one of which has the same hardness as the surface layer and the other of which is softer than the surface layer.

Abstract: A sputtering deposition wherein high aspect ratio apertures are coated with conductive films exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator is used having an aspect ratio that approximates the aspect ratio of the apertures. The resulting film thickness at the bottom of the aperture is at least 2.times. what can be achieved using conventional sputtering methods. The amount of material deposited at the bottom of the apertures can be further enhanced by elevating the temperature of the substrate (e.g. 450.degree. C.) during the deposition process.