Patents by Inventor James Goss

James Goss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE COMPRESSION OF OBJECTS IN A STORAGE COMPUTE DEVICE
    Publication number: 20160078045
    Abstract: Methods and apparatuses facilitate receiving a command via a host interface of a storage compute device to perform a computation on one or more data objects. The computations producing intermediate objects that are stored in data storage section of the storage compute device. A determination is made to compress and decompress the intermediate objects as they are moved between the data storage section and a compute section based on wear of a storage medium being reduced in response to the compression and decompression. The intermediate objects are compressed and decompressed as they are moved between the data storage section and the compute section in response to the determination.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • ASSOCIATING KEYS WITH DATA AND COMPUTE OBJECTS IN A STORAGE COMPUTE DEVICE
    Publication number: 20160077978
    Abstract: A definition is received of at least one data object and a compute object from a host at a storage compute device. A first key is associated with the at least one data object and a second key is associated with the compute object. A command is received from the host to perform a computation that links the first and second keys. The computation is defined by the compute object and acts on the data object. The computation is performed via the storage compute device using the compute object and the data object in response to the command.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • COMBINING DATA BLOCKS IN A NON-VOLATILE, SOLID-STATE MEMORY
    Publication number: 20160054940
    Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Antoine Khoueir, Ryan James Goss, Jon Trantham, Kevin Gomez, Frank Dropps
  • Variable data recovery scheme hierarchy
    Patent number: 9244766
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: January 26, 2016
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Bruce Douglas Buch, Ryan James Goss, Mark Allen Gaertner, Arvind Sridharan
  • Memory device with variable code rate
    Patent number: 9201728
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: December 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Mark Allen Gaertner, Bruce Douglas Buch, Arvind Sridharan
  • ECC management for variable resistance memory cells
    Patent number: 9164832
    Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Methods and devices to increase memory device data reliability
    Patent number: 9164830
    Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 20, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone
  • Transfer unit management
    Patent number: 9164837
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Bruce Douglas Buch, Ryan James Goss
  • Restoring virtualized GCU state information
    Patent number: 9122593
    Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: September 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Scott Seekins, Mark Allen Gaertner
  • Command Execution Using Existing Address Information
    Publication number: 20150234741
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Kris Conklin, Bruce Dunlop, Mark Allen Gaertner, Ryan James Goss
  • Defining address ranges used to cache speculative read data
    Patent number: 9104578
    Abstract: A host read request affects a request address range of a main storage. A speculative address range proximate to the request address range is defined. Speculative data stored in the speculative address range is not requested via the host read request. A criterion is determined that is indicative of future read requests of associated with the speculative data. The speculative data is copied from the main storage to at least one of a non-volatile cache and a volatile cache together with data of the host read request in response to the criterion meeting a threshold. The non-volatile cache and the volatile cache mirror respective portions of the main storage.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: August 11, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: James David Sawin, Luke William Friendshuh, Sumanth Jannyavula Venkata, Ryan James Goss, Mark Allen Gaertner
  • Forming a characterization parameter of a resistive memory element
    Patent number: 9105360
    Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 11, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, Antoine Khoueir, David Scott Ebsen, Jon D. Trantham
  • Non-volatile write buffer data retention pending scheduled verification
    Patent number: 9076530
    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: July 7, 2015
    Assignee: Seagate Technology LLC
    Inventors: Kevin Arthur Gomez, Ryan James Goss, Antoine Khoueir, David Scott Ebsen, Jon D. Trantham
  • METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY
    Publication number: 20150187413
    Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 2, 2015
    Inventors: Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • Optimization of variable resistance memory cells
    Patent number: 9064563
    Abstract: A data storage device may generally be constructed and operated with at least one variable resistance memory cell configured with non-factory operational parameters by a controller. The non-factory operational parameters are assigned in response to an identified variance from a predetermined threshold in at least one variable resistance memory cell.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: June 23, 2015
    Assignee: Seagate Technology LLC
    Inventors: Antoine Khoueir, Mark Allen Gaertner, Ryan James Goss
  • Applying a bias signal to memory cells to reverse a resistance shift of the memory cells
    Patent number: 9058869
    Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: June 16, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Antoine Khoueir, Ryan James Goss, Jon D. Trantham
  • Allocating memory usage based on quality metrics
    Patent number: 9058281
    Abstract: A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: June 16, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, David Scott Seekins, Mark Allen Gaertner
  • Using ECC data for write deduplication processing
    Patent number: 9043668
    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 26, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, Jon D. Trantham
  • Restoring Virtualized GCU State Information
    Publication number: 20150143039
    Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 21, 2015
    Inventors: Ryan James Goss, David Scott Seekins, Mark Allen Gaertner
  • Decomposition chamber
    Patent number: 9021794
    Abstract: According to one embodiment, described herein is an apparatus for decomposing diesel exhaust fluid into ammonia for an internal combustion engine (ICE) system having a selective catalytic reduction system. The apparatus includes an outlet cover, an inlet cover coupled to the outlet cover, and a support plate disposed between the outlet cover and the inlet cover. The support plate forms an outlet channel with the outlet cover and an inlet channel with the inlet cover. The inlet channel is fluidly coupled to the outlet channel. Additionally, the inlet channel may be adjacent to the outlet channel.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Cummins Intellectual Property, Inc.
    Inventors: James Goss, Duncan Engeham, Ryan M. Johnson