Patents by Inventor James Goss

James Goss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Applying a bias signal to memory cells to reverse a resistance shift of the memory cells
    Patent number: 9025359
    Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 5, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Antoine Khoueir, Ryan James Goss, Jon D. Trantham
  • Command execution using existing address information
    Patent number: 9026699
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Seagate Technology LLC
    Inventors: Kris Conklin, Bruce Dunlop, Mark Allen Gaertner, Ryan James Goss
  • SYSTEM AND METHOD FOR TRANSFERRING WIRELESS NETWORK ACCESS PASSWORDS
    Publication number: 20150094027
    Abstract: The present disclosure provides an access node for transferring and/or assigning network passwords. The access node includes a first interface for sending and receiving communication of a first type to and from a first node operating in a wireless local area network (WLAN). The access node also includes a second interface for sending and receiving communication of a second type to and from a second node in a mobile network, such as a GSM/GPRS network. The access node further includes a short messaging service (SMS) module for sending and receiving. SMS messages to the second node carrying an OTP allocated. The access node also includes a mechanism to verify a precondition before the OTP is sent to the second node.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 2, 2015
    Inventors: Yong ZHOU, Prasanna J. SATARASINGHE, David Ka-Wai HUI, Vladimir ALPEROVICH, James GOSS, John BAKER
  • VARIABLE DATA RECOVERY SCHEME HIERARCHY
    Publication number: 20150089278
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: Seagate Technology LLC
    Inventors: Ara Patapoutian, Bruce Douglas Buch, Ryan James Goss, Mark Allen Gaertner, Arvind Sridharan
  • COMMAND EXECUTION USING EXISTING ADDRESS INFORMATION
    Publication number: 20150089119
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: Seagate Technology LLC
    Inventors: Kris Conklin, Bruce Dunlop, Mark Allen Gaertner, Ryan James Goss
  • Memory Device with Variable Code Rate
    Publication number: 20150074487
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Seagate Technology LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Mark Allen Gaertner, Bruce Douglas Buch, Arvind Sridharan
  • TRANSFER UNIT MANAGEMENT
    Publication number: 20150074486
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Bruce Douglas Buch, Ryan James Goss
  • Limiting activity rates that impact life of a data storage media
    Patent number: 8954689
    Abstract: A first cumulative data transfer over a first time window from an intermediary module to a data storage media is determined. The intermediary module is coupled between a host interface and the data storage media. An activity rate from the intermediary module to the data storage media is limited for one or more subsequent time windows if the first cumulative activity rate exceeds a threshold value that impacts life of the data storage media. The limitation of the activity rate is removed after the one or more subsequent time windows expire.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 10, 2015
    Assignee: Seagate Technology LLC
    Inventors: David Scott Seekins, Ryan James Goss, Kristofer Carlson Conklin
  • Restoring virtualized GCU state information
    Patent number: 8938597
    Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: January 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Scott Seekins, Mark Allen Gaertner
  • Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory
    Patent number: 8934284
    Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • Background deduplication of data sets in a memory
    Patent number: 8930612
    Abstract: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 6, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, David Scott Seekins
  • Multi-level cell (MLC) update with protected mode capability
    Patent number: 8923045
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a first block of data is written to a group of memory cells at a first memory location in single-level cell (SLC) mode. The first block of data is copied from the first memory location to a group of memory cells at a second memory location to provide a backup copy of the first block of data during a protected mode of operation. A second block of data is subsequently overwritten to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 30, 2014
    Assignee: Seagate technology LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, David Scott Seekins
  • Secure erasure of data from a non-volatile memory
    Patent number: 8909888
    Abstract: Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: December 9, 2014
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Scott Seekins, Jonathan W. Haines, Timothy R. Feldman
  • System and method for transferring wireless network access passwords
    Patent number: 8885555
    Abstract: The present disclosure provides an access node for transferring and/or assigning network passwords. The access node includes a first interface for sending and receiving communication of a first type to and from a first node operating in a wireless local area network (WLAN). The access node also includes a second interface for sending and receiving communication of a second type to and from a second node in a mobile network, such as a GSM/GPRS network. The access node further includes a short messaging service (SMS) module for sending and receiving. SMS messages to the second node carrying an OTP allocated. The access node also includes a mechanism to verify a precondition before the OTP is sent to the second node.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Yong Zhou, Prasanna J. Satarasinghe, Vladimir Alperovich, David Ka-Wai Hui, James Goss, John Baker
  • Management of variable resistance data storage device
    Patent number: 8879302
    Abstract: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 4, 2014
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Ryan James Goss, Jon D. Trantham
  • DECOMPOSITION CHAMBER
    Publication number: 20140260209
    Abstract: According to one embodiment, described herein is an apparatus for decomposing diesel exhaust fluid into ammonia for an internal combustion engine (ICE) system having a selective catalytic reduction system. The apparatus includes an outlet cover, an inlet cover coupled to the outlet cover, and a support plate disposed between the outlet cover and the inlet cover. The support plate forms an outlet channel with the outlet cover and an inlet channel with the inlet cover. The inlet channel is fluidly coupled to the outlet channel. Additionally, the inlet channel may be adjacent to the outlet channel.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: CUMMINS INTELLECTUAL PROPERTY, INC.
    Inventors: James Goss, Duncan Engeham, Ryan M. Johnson
  • SELECTING BETWEEN NON-VOLATILE MEMORY UNITS HAVING DIFFERENT MINIMUM ADDRESSABLE DATA UNIT SIZES
    Publication number: 20140281280
    Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, Jon D. Trantham, Antoine Khoueir, David Scott Ebsen, Mark Allen Gaertner, Kevin Gomez
  • FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT
    Publication number: 20140258646
    Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, Antoine Khoueir, David Scott Ebsen, Jon D. Trantham
  • Self-initiated secure erasure responsive to an unauthorized power down event
    Patent number: 8832402
    Abstract: Method and apparatus for self-initiated secure erasure of data from a non-volatile memory, such as a solid state drive (SSD). In accordance with various embodiments, the memory is operated in communication with a host device. A self-initiated, non-destructive secure erasure of the data stored in the memory is carried out responsive to a detection of an unauthorized power down event associated with the memory.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Scott Seekins
  • METHODS AND APPARATUSES USING A TRANSFER FUNCTION TO PREDICT RESISTANCE SHIFTS AND/OR NOISE OF RESISTANCE-BASED MEMORY
    Publication number: 20140241032
    Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Antoine Khoueir