Abstract: A complex test structure for integrated, semiconductor circuits in which the impurity regions of the test device are elongated, preferably in serpentine fashion. The elongated impurity regions emulate corresponding regions in regular integrated circuit devices. Additional regions are provided, each in elongated form, which, when impressed with appropriate voltages or currents, provide indications of defect levels and product yield in the regular devices. Advantageously, the serpentine test structure is fabricated on the same wafer and with the same process steps as the regular integrated circuit chips. In one embodiment, a plurality of such monitors are provided adjacent each other in the same test site. Regions in one monitor are selectively connected to regions in another monitor and to external contact pads by contact stations disposed between each monitor.

Abstract: A semiconductor defect monitoring structure employs a series of electrically testable serpentine stripe patterns having different widths and spacing in order to determine the distribution of the density of defects by size. Metal stripe patterns are superposed and rotated 90.degree. with respect to diffusion stripe patterns in a semiconductor wafer. A set of four field effect transistor devices are connected to each stripe pattern in such a way that tests may be made for all defects without interference between adjacent patterns. The defect monitoring structure helps to determine defects such as opens in diffusion and metallization, shorts in metallization, shorts in diffusion, pinholes in a thin oxide, and pinholes in a thick oxide.