Abstract: Accessing control means and methods are provided for controlling the granting of access by a plurality of requestors to a commonly shared unit on a predetermined priority basis. An addressable programmed memory, such as a ROM, is programmed to provide a predetermined access priority. The ROM operates in response to sequentially applied addresses to produce ROM outputs which determine the manner in which access is granted to the requestors. Each ROM output also includes history outputs which are fed back and combined with requestor signals to form each ROM address, whereby requestor access grating selection is determined based on previous access granting history as well as on current request status.

Abstract: A novel memory access system is provided for simultaneously processing request for access to a plurality of memory banks. A plurality of input-output ports are coupled to a read bus and to a write bus which are in turn coupled to the memory banks to be accessed by read and write commands initiated by processors coupled to the I/O ports. Pipeline control means receive the request for access functions from the processors and are operable to resolve conflict between plural request. The pipeline control means sequentially raise either write or read request on control and address buses and generate time slot windows during which subsequent write or read data transfer operations will occur so that data being pipelined on the write and read buses is being simultaneously accessed.

Abstract: Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.

Abstract: A memory system which is shared by a plurality of requestors each of which supply read and write address bits to the memory system is read out of, or written into, in accordance with read and write address bits. A sequencer is utilized to initiate a sequence of timing signals that control the reading, writing and partial writing of data. Certain ones of these signals occur at fixed intervals from the receipt of an initial load address signal. A read address circuit coupled to receive the read address bits generates a set of check bits. A read address stack means stores each set of read address check bits upon the occurrence of an associated load read address stack signal. A write address check bit generator means is coupled to receive write address bits and to generate a set of check bits representative of the write address bits. A write address stack means stores each set of the write address check bits upon the occurrence of an associated load write address stack signal.

Abstract: A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.

Abstract: A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Abstract: An error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines. Utilizing this type of DRAM, the memory system employs controls, input, output and read circuitry to read bits out of the memory via the output circuitry and write circuitry to write bits into the memory via the input circuitry. An error checking and correction circuit is coupled to the output means which includes a check bit generator and a syndrome generator, and a control means energizes the error checking and correcting means during the write cycle, as well as the read cycle, so that the errors are detected during the write cycle as well as the read cycle. In this manner, errors which occur in circuitry other than the memory, which includes the memory driving and reading logic and also the check bit generator logic translators and syndrome generators, may be separately detected from memory errors.

Abstract: A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A Start Bit Code defines the location of the start of the bit field to be written and an End Bit Code defines the bit after the last bit that is to be merged and written. Write and Read Data to be used in the partial merge operation are stored in a Merge Register along with a code derived from the Start and End Code bits. The bits not used are stored in a Non-Merge Register. Parities are compared to verify that a parity error did not occur when the Merge Register was loaded.

Abstract: A multibank computer memory system is provided in which the storage banks monitor the initiate line while each bank operation is being processed to verify that another initiate is not received before it can be processed. This serves to check that the control logic is not in error, and that there is no error between the control section and the banks.

Abstract: A virtual stack structure utilizing Write Pointers and Read Pointers for providing pipelined data words on a first-in first-out basis to a memory structure is described. The virtual stack structure incorporates a plurality of Stack Registers each having an unique Write Tag and Read Tag associated therewith. The Write Tags are utilized to through-check the decoding of the Write Pointer and to issue Write Tag Error signals when it is determined that the Write Pointer has been improperly decoded. Circuitry is provided for checking the appropriate loading of the Write Pointer in the stack, and issuing an error signal when improper loading is sensed. Each of the Stack Registers has an unique Read Tag associated therewith that is utilized to through-check the decoding of the Read Pointer and to issue Read Tag Error signals when improper decoding is detected.

Abstract: The preferred embodiment shown involves forming the memory system of B memory banks, where B is preferably a prime number, but may be a nonbinary number, i.e., B=2.sup.X, where X is a positive integer, and where the requested address=(Q+R)B. The address translation system for each requestor seeking access to the memory system includes a ROM and an adder. The ROM is comprised of two ROMs, Q ROMa and Q ROMb. ROMb stores in successive memory locations a first portion Qb of the memory system address and Q ROMa stores in successive memory locatins a second portion Qa of the memory system address. An adder sums the data, Qa+Qb, stored in the addressed memory locations of Q ROMa and Q ROMb while Q ROMa stores in successive memory locations a Bank R portion that specifies the one of the B banks in which the sum Qa+Qb addresses the selected memory address in the selected memory bank of the memory system.

Abstract: A Multiple Unit Adapter is disclosed which provides a high speed interface between a single Scientific Processor and a plurality of High Performance Storage Units. This Multiple Unit Adapter is required only when more than one High Performance Storage Unit is used in the data processing system. Since the Scientific Processor of the data processing system is configured with only a single High Performance Storage Unit port its design is simplified and, of course, its cost is reduced. This is especially so when the data processing system uses only a single High Performance Storage Unit. It therefore enables the data processing system to be expanded into a system having a larger memory capacity while keeping the design of the Scientific Processor constant, less complex and consequently less costly.

Abstract: An improved partially duplicated stack structure for ensuring data integrity through a pipelined stack is described. An improved virtual first-in first-out stack structure having a plurality of parallel stacks, each for storing predetermined segments of data signals from a total data word is described in conjunction with one or more associated compare stack structures which are commonly accessed during loading and reading the stack. The compare stack is arranged for storing predetermined selected bit groupings associated with each of the segments of data signals. The bit groupings from the compare stack are compared with like-situated bit groupings from the associated segments of data signals at readout. Failure of the bit-by-bit comparison results in an indication that a stack address decode error has occurred, thereby providing through-checking of the integrity of the functioning of the stack structures.

Abstract: Within a High Performance Storage Unit (HPSU) digital memory resource, plural ones (up to 4) of a multiplicity (nominally 8) of independently operative storage memory banks, each consisting of four storage modules, are each simultaneously communicating voluminous read data (nominally 144 data bits plus 16 parity bits) read from each to a respective one of plural (nominally 4) output ports of the memory resource, said communicating being upon and via a selected one of a like plural number (4) of wired-OR communication buses.

Abstract: An improved multiple port memory system has a priority network for selecting between multiple units seeking access thereto. The priority network responds to requests for access and provides encoded port identifying signals indicative of the port to have access. Decode circuitry decodes the encoded port identifying signals and provides unique port enabling signals for the selected port. Decode error detection circuitry responds to the decoded port enabling signals and provides a decode error indication any time multiple port enabling signals are detected as occurring simultaneously. Port Code error detecting circuitry respond to the encoded port identifying signals and the decoded port enabling signals to provide a code error indicating signal when a port code error condition is detected.

Abstract: A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors.

Abstract: A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: For use with a digital memory system that generates error correction code signals for storage with associated data words and for correction of detected error(s) in the associated data words when accessed, a system for through checking the accuracy of generation of the error correction codes and the decoding of error correction code is described. A data word parity signal is generated for storage with the associated data word and its associated check bit. When a data word is accessed, the read data word and its associated check bits are applied to error correction circuitry that results in a determination of whether or not any bits of the read data word are in error. Correction circuitry corrects those error in the read data word that are correctable. The corrected read data word is applied to a parity generator circuit that generates that parity of the corrected read data word. A comparison circuit compares the word parity calculated for the corrected read data word.

Abstract: A memory array having a dedicated refresh flag memory (RFM) for maintaining a record of the array's addresses that are accessed during a refresh requirement interval (RRI) and means for reading the RFM during the RRI and refreshing those array addresses which weren't accessed during the operating interval of the RRI. The refresh operation being performed in a "burst" mode or in an "interleaved" mode during the RRI.

Abstract: A memory system which already includes an address register, a randomly accessible memory unit, a data-in register and a data-out register is converted to also include a one word buffer memory with the addition of only a few components. A plus one adder is included for incrementing the address contained in the address register and the result is then stored in an address plus one register. The randomly accessible memory unit may be accessed with the address plus one register when it has completed the normal access with the address register pending a new request. The resultant memory data from this access at the incremented address is stored in a one word internal register which is a buffer to the randomly accessible memory unit. Since such access is noninterfering with and overlapped in time with the overall memory system communication with a requestor, and pending any new request to the randomly accessible memory stores, it serves to efficiently create a buffer store only for the next consecutive address.