Abstract: An article of footwear, such as a shoe, includes an upper and a sole. The upper may be formed with an outer layer and a floating textile layer relative to one or more portions of the outer layer. The floating textile layer has an apparent elongation that is less than an apparent elongation of the outer layer in response to an equal tensile force applied to each of the floating textile layer and the outer layer along a same axis of orientation. The differential in apparent elongation of the outer layer and the floating textile layer may increase wearability and functionability of the upper.

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Abstract: An article of footwear, such as a shoe, includes an upper and a sole. The upper may be formed with an outer layer and a floating textile layer relative to one or more portions of the outer layer. The floating textile layer has an apparent elongation that is less than an apparent elongation of the outer layer in response to an equal tensile force applied to each of the floating textile layer and the outer layer along a same axis of orientation. The differential in apparent elongation of the outer layer and the floating textile layer may increase wearability and functionability of the upper.

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Abstract: An article of footwear, such as a shoe, includes an upper and a sole. The upper may be formed with an outer layer and a floating textile layer relative to one or more portions of the outer layer. The floating textile layer has an apparent elongation that is less than an apparent elongation of the outer layer in response to an equal tensile force applied to each of the floating textile layer and the outer layer along a same axis of orientation. The differential in apparent elongation of the outer layer and the floating textile layer may increase wearability and functionability of the upper.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: Event tracing for a system-on-chip (SOC) may be implemented by instrumenting, using a computer, a design for the SOC with instrumentation program code that, responsive to execution by a processor of the SOC, generates software trace events. The design may be specified in a high level programming language. A circuit design specifying an accelerator circuit for a function of the design may be generated using the computer. The accelerator circuit is configured for implementation within programmable circuitry of the SOC. The circuit design may be instrumented to include trace circuitry using the computer. The trace circuitry may be configured to detect hardware trace events for operation of the accelerator circuit, receive the software trace events, and combine the hardware and software trace events into time synchronized trace data.

Abstract: A manufacturing method of a glass fiber product is disclosed. A glass fiber resin is provided. The glass fiber resin includes a thermoplastic resin, a glass fiber, and an additive. The amount of the thermoplastic resin is between 30 wt % and 70 wt %, the content of the glass fiber is between 40 wt % and 70 wt % and the amount of the additive is between 0.1 wt % and 15 wt %. A molding process is performed for the glass fiber resin to mold the glass fiber resin into a semi-finished product. A mechanical machining process is performed on the semi-finished product to form at least one recessed structure in the semi-finished product, so as to form a final product.

Abstract: An article of footwear, such as a shoe, includes an upper and a sole. The upper may be formed with an outer layer and a floating textile layer relative to one or more portions of the outer layer. The floating textile layer has an apparent elongation that is less than an apparent elongation of the outer layer in response to an equal tensile force applied to each of the floating textile layer and the outer layer along a same axis of orientation. The differential in apparent elongation of the outer layer and the floating textile layer may increase wearability and functionability of the upper.

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

Abstract: An upper for an article of footwear may have material layers and a plurality of strand segments. The material layers are located adjacent to each other and in an overlapping configuration, and the material layers are located in a lace region and a lower region of the upper. The strand segments extend from the lace region to the lower region. The strand segments may be located and secured between the material layers in the lace region and the lower region. The strand segments may form both an exterior surface of the upper and an opposite interior surface of the upper in an area between the lace region and the lower region. The material layers may define an opening between the lace region and the lower region, and the strand segments extend across the opening.

Abstract: A luminaire and method of installing same on a mounting pole including a housing having a flange and a plurality of LEDs. The flange includes formed therein a plurality of spaced apart holes disposed along a line, a slot disposed along the line, and a central hole disposed along the line and between the slot and the spaced apart holes. The plurality of LEDs are attached to or disposed in the housing. The method includes hanging the luminaire on an upper mounting bolt extending from a mounting pole, sliding the upper mounting bolt along the slot so that a conduit hole and the central hole are at least partially aligned to each other and one of the plurality of spaced apart holes is aligned to a lower mounting hole, and installing a lower mounting bolt through a lower mounting hole and the one spaced apart hole aligned therewith.

Abstract: A manufacturing method of a glass fiber product is disclosed. A glass fiber resin is provided. The glass fiber resin includes a thermoplastic resin, a glass fiber, and an additive. The amount of the thermoplastic resin is between 30 wt % and 70 wt %, the content of the glass fiber is between 40 wt % and 70 wt % and the amount of the additive is between 0.1 wt % and 15 wt %. A molding process is performed for the glass fiber resin to mold the glass fiber resin into a semi-finished product. A mechanical machining process is performed on the semi-finished product to form at least one recessed structure in the semi-finished product, so as to form a final product.

Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

Abstract: An article of footwear may have a sole structure and an upper that includes a foundation element, a tensile strand, and a securing strand. The tensile strand is located adjacent to an exterior surface of the foundation element and substantially parallel to the exterior surface for a distance of at least five centimeters. The securing strand joins or secures the tensile strand to the foundation element. Although the thicknesses may vary, a thickness of the tensile strand may be at least three times the thickness of the securing strand. In some configurations, a backing strand may also assist with joining the securing strand to the foundation element.