Patents by Inventor James Hadley

James Hadley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Managing Multiple Threads In A Single Pipeline
    Publication number: 20130013898
    Abstract: In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a pipestage of a pipeline, and if so, dispatching an instruction of a second thread from a second queue associated with the second thread to the pipeline if the second thread is not stalled. Other embodiments are described and claimed.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Inventors: Matthew Merten, Avinash Sodani, James Hadley, Alexander Farcy, Iredamola Olopade
  • PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
    Publication number: 20110055524
    Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Inventors: Morris Marden, Matthew Merten, Alexandre Farcy, Avinash Sodani, James Hadley, Ilhyun Kim
  • PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR
    Publication number: 20110055525
    Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Inventors: Morris Marden, Matthew Merten, Alexandre Farcy, Avinash Sodani, James Hadley, Ilhyun Kim
  • Providing thread fairness in a hyper-threaded microprocessor
    Publication number: 20080250233
    Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
    Type: Application
    Filed: April 9, 2007
    Publication date: October 9, 2008
    Inventors: Morris Marden, Matthew Merten, Alexandre Farcy, Avinash Sodani, James Hadley, Ilhyun Kim
  • Managing multiple threads in a single pipeline
    Publication number: 20080082796
    Abstract: In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a pipestage of a pipeline, and if so, dispatching an instruction of a second thread from a second queue associated with the second thread to the pipeline if the second thread is not stalled. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Matthew Merten, Avinash Sodani, James Hadley, Alexandre Farcy, Iredamola Olopade
  • Early misprediction recovery through periodic checkpoints
    Publication number: 20070043934
    Abstract: Methods and apparatus to provide misprediction recovery through periodic checkpoint are described. In one embodiment, a renamer unit (e.g., within a processor core) recovers a register alias table (RAT) to a state immediately preceding a misprediction.
    Type: Application
    Filed: August 22, 2005
    Publication date: February 22, 2007
    Inventors: Avinash Sodani, James Hadley