Abstract: Provided is a food composition which include a myceliated high-protein food product and methods to make such compositions, which are mixtures of myceliated high-protein food products and other edible materials. A food composition includes dairy alternative products, ready to mix beverages and beverage bases; extruded and extruded/puffed products; sheeted baked goods; meat analogs and extenders; baked goods and baking mixes; granola; and soups/soup bases. Food compositions also include texturized plant protein which can be used for making meat-structured plant protein meat analog or meat extender products. The food compositions have reduced undesirable flavors and reduced undesirable aromas due to use of myceliated high-protein food products as compared to use of similar high-protein material that is not myceliated.

Abstract: An electric motor is provided including a stator, a rotor, a motor spindle coupled to the rotor and extending along a center axis, a first end cap formed on a first side of the stator, a second end cap formed on a second side of the stator and secured to the first end cap to form a first compartment around the stator and the rotor, an electro-magnetic brake module disposed on a side of the second end cap opposite the stator and engaged with the motor spindle, and a motor cover mounted on the second end cap to form a second compartment around the electro-magnetic brake module. The first end cap, the second end cap, and the motor cover form a substantially watertight seal around the stator, the rotor, and the position sensor assembly.

Abstract: An electric power apparatus includes a main planar body having a circular opening that supports a brushless direct-current (BLDC) motor. The motor includes a stator, a rotor, a motor spindle extending through the circular opening, a first end cap formed on a first side of the stator and mounted on the main planar body; and a second end cap formed on a second side of the stator and secured to the first end cap to form a substantially watertight seal around the stator and the rotor. A ratio of a maximum power output of the motor when powered by at least one battery pack to a height of the motor as measured from an upper surface of the main planar body to a top surface of the motor is greater than or equal to approximately 34 watts/mm.

Abstract: Techniques for interconnecting chips using a bridge chip having through vias is provided. In one aspect, a structure includes: a bridge chip attached to at least a first chip and a second chip, wherein the bridge chip has at least one conductive through via connecting the bridge chip to one of the first chip and the second chip. The bridge chip can include a wiring layer having metal lines present between a first capping layer and a second capping layer, and the at least one conductive through via can directly contact at least a sidewall of at least one of the metal lines. A method of integrating chips using the present bridge chip is also provided.

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Abstract: A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

Abstract: Techniques for interconnecting chips using a bridge chip having through vias is provided. In one aspect, a structure includes: a bridge chip attached to at least a first chip and a second chip, wherein the bridge chip has at least one conductive through via connecting the bridge chip to one of the first chip and the second chip. The bridge chip can include a wiring layer having metal lines present between a first capping layer and a second capping layer, and the at least one conductive through via can directly contact at least a sidewall of at least one of the metal lines. A method of integrating chips using the present bridge chip is also provided.

Abstract: A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer.

Abstract: A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

Abstract: A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer.

Abstract: Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs.

Abstract: Various methods and structures for fabricating BEOL metallization layer including at least one bulk cobalt contact, the at least one bulk cobalt contact including a replacement non-cobalt metal cap integral to the at least one bulk cobalt contact. The method includes performing selective deposition, by a chemical exchange reaction of metal between a non-cobalt metal and Cobalt in the at least one bulk cobalt contact, of the replacement non-cobalt metal cap integrally formed in a top surface region of the bulk cobalt contact.

Abstract: Copper (Cu)-to-Cu bonding techniques for high bandwidth interconnects on a bridge chip attached to chips which are further attached to a packaging substrate are provided. In one aspect, a method of forming an interconnect structure is provided. The method includes: bonding individual chips to at least one bridge chip via Cu-to-Cu bonding to form a multi-chip structure; and bonding the multi-chip structure to a packaging substrate via solder bonding, after the Cu-to-Cu bonding has been performed, to form the interconnect structure including the individual chips bonded to the at least one bridge chip and to the packaging substrate. A structure formed by the method is also provided.

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Abstract: Techniques for simultaneously plating features of varying sizes on a semiconductor substrate are provided. In one aspect, a method for electroplating includes: placing a shield over a wafer, offset from a surface of the wafer, which covers portions of the wafer and leaves other portions of the wafer uncovered; and depositing at least one metal onto the wafer by electroplating to simultaneously form metallurgical features of varying sizes on the wafer based on the shield altering local deposition rates for the portions of the wafer covered by the shield. An electroplating apparatus is also provided.

Abstract: A method for fabricating a semiconductor device includes forming first and second interconnect levels on a substrate with the first and second interconnect levels having respective first and second dielectric layers and first and second patterned metal conductors and where each of the first and second patterned metal conductors includes a first metallic material, depositing a third dielectric layer onto the second first interconnect layer, forming a via opening extending through the third dielectric layer and the second dielectric layer and connecting with the first patterned metal conductor of the first interconnect level and depositing a second metallic material different from the first metallic material into the via opening to form a via The via electrically couples with the patterned metal layer of the first interconnect level.

Abstract: A semiconductor device structure includes an MRAM metallization stack. A via is disposed within a dielectric cap layer that is on and in contact with the metallization stack. A liner is disposed on sidewalls and a bottom surface of the via. A recessed electrode contact is disposed within a portion of the via and in contact with a first part of the liner in contact with sidewalls of the via. A second part of the liner is in contact with the sidewalls is above a top surface of the contact. A method for forming the semiconductor device structure includes forming a via within a MRAM metallization stack. The via exposes a top surface of the second metal layer. An electrode contact is formed within a portion of the via. A cap layer is formed within a remaining portion of the via in contact with a top surface of the electrode contact.

Abstract: A method of forming a semiconductor structure includes the following steps. At least a first source/drain region and a second source/drain region are formed in a substrate. At least a first sacrificial layer and a second sacrificial layer are respectively formed over the first source/drain region and the second source/drain region. A spacer layer is formed on at least a top surface of the substrate and around sides of the first sacrificial layer and the second sacrificial layer. The spacer layer includes an electrical-isolating material. The first sacrificial layer and a second sacrificial layer are removed to form a first open trench and a second open trench. The first open trench and the second open trench are filled with metal contact material to form a first metal contact and a second metal contact electrically isolated from each other by the spacer layer.

Abstract: Techniques for simultaneously plating features of varying sizes on a semiconductor substrate are provided. In one aspect, a method for electroplating includes: placing a shield over a wafer, offset from a surface of the wafer, which covers portions of the wafer and leaves other portions of the wafer uncovered; and depositing at least one metal onto the wafer by electroplating to simultaneously form metallurgical features of varying sizes on the wafer based on the shield altering local deposition rates for the portions of the wafer covered by the shield. An electroplating apparatus is also provided.