Patents by Inventor James J. Murphy

James J. Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240352650
    Abstract: A removable fluid pumping and filtration apparatus for a laundry treatment machine is provided. The apparatus includes a handle portion. A filter section is configured to selectively couple to an impeller of the laundry treatment machine, the filter section defining a hollow interior, a lower water opening to allow for the passage of water out of the interior space of the agitator, and an opening about the exterior circumference of the filter section into which a removable filter is selectively attachable. A handle pull locking post is provided within the hollow interior of the apparatus, including a handle pull portion at a top end for gripping against the handle portion and at least one pin at a bottom end configured to selectively lock the apparatus into the base.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Anup Sudhir BHAVSAR, Jalindar Suresh DAWANGE, Gregory R. FULMER, James D. JEFFERY, Benjamin D. LOWELL, Eric W. MERROW, Sayer J. MURPHY, Nicholas C. SCHOOLEY, Thomas D. SPICER, Jon D. STRAIT, Eric J. VASKO, Heather A. HELLMUTH, Michael A. LEDFORD, Meagan K. VANDERVELDE
  • Publication number: 20240299353
    Abstract: Disclosed herein is a method of treating a substance use disorder in a subject suffering from sustained substance exposure, comprising: administering to the subject a therapeutically effective amount of 5-methoxy-N,N-dimethyltryptamine (5-MeO-DMT), or a pharmaceutically acceptable derivative or salt thereof.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 12, 2024
    Inventors: Keith J. MURPHY, James LINDEN
  • Patent number: 12085066
    Abstract: A pulsatile fluid pump system includes a pump-valving assembly including a chamber and a diaphragm assembly coupled to the chamber and including a flexible diaphragm. The diaphragm assembly and the pump-valving assembly are configured as an integral pump assembly. The system further includes a linear motor having a magnet and a coil, the magnet moving in relation to the coil, the coil having an electrical input. The system also includes a control housing rigidly coupled to the linear motor and a controller system having an electrical output coupled to the electrical input of the coil, the controller system defining an electrical waveform at the electrical output to cause desired operation of the diaphragm. The integral pump assembly is configured to be removably coupled to the control housing, and the diaphragm assembly of the integral pump assembly is configured to be removably coupled to the linear motor.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 10, 2024
    Assignee: VentriFlo, Inc.
    Inventors: Douglas E. Vincent, Brian Bailey, Conrad Bzura, David Butz, David Olney, Eric Smith, George Koenig, James W. Poitras, Jeffrey P. Naber, Judy Labonté, Kathleen Vincent, Lawrence Kuba, Matthew J. Murphy, Patrick Shields, Roger Greeley
  • Publication number: 20240254097
    Abstract: The present disclosure provides processes for the production of 2-5-furandicarboxylic acid (FDCA) and intermediates thereof by the chemocatalytic conversion of a furanic oxidation substrate. The present disclosure further provides processes for preparing derivatives of FDCA and FDCA-based polymers. In addition, the present disclosure provides crystalline preparations of FDCA, as well as processes for making the same.
    Type: Application
    Filed: December 20, 2023
    Publication date: August 1, 2024
    Inventors: Valery Sokolovskii, Vincent J. Murphy, Thomas R. Boussie, Gary M. Diamond, Eric L. Dias, Guang Zhu, James M. Longmire, Stanley Herrmann, Staffan Torssell, Mayya Lavrenko
  • Patent number: 12043944
    Abstract: A removable fluid pumping and filtration apparatus for a laundry treatment machine is provided. The apparatus includes a handle portion. A filter section is configured to selectively couple to an impeller of the laundry treatment machine, the filter section defining a hollow interior, a lower water opening to allow for the passage of water out of the interior space of the agitator, and an opening about the exterior circumference of the filter section into which a removable filter is selectively attachable. A handle pull locking post is provided within the hollow interior of the apparatus, including a handle pull portion at a top end for gripping against the handle portion and at least one pin at a bottom end configured to selectively lock the apparatus into the base.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: July 23, 2024
    Assignee: WHIRLPOOL CORPORATION
    Inventors: Anup Sudhir Bhavsar, Jalindar Suresh Dawange, Gregory R. Fulmer, James D. Jeffery, Benjamin D. Lowell, Eric W. Merrow, Sayer J. Murphy, Nicholas C. Schooley, Thomas D. Spicer, Jon. D. Strait, Eric J. Vasko, Heather A. Hellmuth, Michael A. Ledford, Meagan K. Vandervelde
  • Patent number: 8936985
    Abstract: A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: January 20, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
  • Patent number: 8598035
    Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 3, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Douglas E. Dolan
  • Patent number: 8343852
    Abstract: A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: January 1, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Minhua Li, Qi Wang, Gordon Sim, Matthew Reynolds, Suku Kim, James J. Murphy, Hamza Yilmaz
  • Patent number: 8329538
    Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, James J. Murphy
  • Patent number: 8329508
    Abstract: A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: December 11, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Steven Sapp, Qi Wang, Minhua Li, James J. Murphy, John Robert Diroll
  • Publication number: 20120220091
    Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
    Type: Application
    Filed: March 12, 2012
    Publication date: August 30, 2012
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Publication number: 20120168947
    Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
    Type: Application
    Filed: February 24, 2012
    Publication date: July 5, 2012
    Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
  • Patent number: 8198196
    Abstract: A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: June 12, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James J. Murphy, Hui Chen, Eileen Valdez
  • Publication number: 20120142155
    Abstract: A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench.
    Type: Application
    Filed: June 6, 2011
    Publication date: June 7, 2012
    Inventors: James J. MURPHY, Hui CHEN, Eileen VALDEZ
  • Patent number: 8158506
    Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: April 17, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
  • Patent number: 8143124
    Abstract: A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ashok Challa, Alan Elbanhawy, Dean E. Probst, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Becky Losee, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher B. Kocon, Debra S. Woolsey
  • Patent number: 8143125
    Abstract: A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert J. Purtell, James J. Murphy
  • Patent number: 8129778
    Abstract: Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: March 6, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Suku Kim, James J. Murphy, Gary Dolny
  • Patent number: 8058732
    Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: November 15, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Ihsiu Ho, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Rohit Dikshit
  • Publication number: 20110244641
    Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 6, 2011
    Inventors: James Pan, James J. Murphy