Patents by Inventor JAMES KENT NAYLOR

JAMES KENT NAYLOR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11060183
    Abstract: A coating apparatus may be configured to concurrently receive and waterproof a large number of electronic device assemblies. The coating apparatus may include a track for transporting the electronic device assemblies into an application station. The application station may have a cubic shape, and include an entry door and an opposite exit door. The entry and exit doors may enable the introduction of substrates into the application station, as well as their removal from the application station. In addition, the entry and exit doors may enable isolation of the application station from an exterior environment and, thus, provide control over the conditions under which a moisture resistant material is applied to the substrates. Methods for making electronic devices and other substrates resistant to moisture are also disclosed.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 13, 2021
    Inventors: Dana Cox, Max Sorenson, James Kent Naylor
  • Publication number: 20200208258
    Abstract: An apparatus for applying a protective coating to a high volume of separate electronic device assemblies includes a treatment element that is configured to prepare the high volume of electronic devices before protective coatings are applied to the electronic devices. The apparatus also includes a coating element configured to apply protective coatings to the high volume of separate electronic device assemblies.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Max Sorenson, Blake Stevens, Alan Rae, Marc Kenneth Chason, Dana Cox, James Kent Naylor
  • Patent number: 8592277
    Abstract: A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 26, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
  • Publication number: 20130286567
    Abstract: An apparatus for applying a protective coating to a high volume of separate electronic device assemblies includes a treatment element that is configured to prepare the high volume of electronic devices before protective coatings are applied to the electronic devices. The apparatus also includes a coating element configured to apply protective coatings to the high volume of separate electronic device assemblies.
    Type: Application
    Filed: June 18, 2013
    Publication date: October 31, 2013
    Inventors: Max Sorenson, Blake Stevens, Alan Rae, Marc Kenneth Chason, Dana Cox, James Kent Naylor
  • Publication number: 20130251889
    Abstract: A coating apparatus may be configured to concurrently receive and waterproof a large number of electronic device assemblies. The coating apparatus may include a track for transporting the electronic device assemblies into an application station. The application station may have a cubic shape, and include an entry door and an opposite exit door. The entry and exit doors may enable the introduction of substrates into the application station, as well as their removal from the application station. In addition, the entry and exit doors may enable isolation of the application station from an exterior environment and, thus, provide control over the conditions under which a moisture resistant material is applied to the substrates. Methods for making electronic devices and other substrates resistant to moisture are also disclosed.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 26, 2013
    Applicant: HzO, Inc.
    Inventors: Dana Cox, Max Sorenson, James Kent Naylor
  • Publication number: 20110014763
    Abstract: A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Inventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
  • Publication number: 20100117231
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions.
    Type: Application
    Filed: January 20, 2010
    Publication date: May 13, 2010
    Inventors: Dennis Lang, Sonbol Vaziri, James Kent Naylor, Eric Woolsey, Chung-Lin Wu, Mike Gruenhagen, Neill Thornton
  • Publication number: 20070190728
    Abstract: A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.
    Type: Application
    Filed: August 29, 2006
    Publication date: August 16, 2007
    Inventors: Sreevatsa Sreekantham, Ihsiu Ho, Fred Session, James Kent Naylor
  • Publication number: 20010001733
    Abstract: According to an example embodiment, the present invention is directed to a method for manufacturing a semiconductor device. The device comprises a light-reflective layer and an anti-reflective coating layer over the light-reflective layer. A material is located over the anti-reflective coating layer. The semiconductor is selectively etched using a non-polymerizing oxygen-rich fluorocarbon chemistry. By using an oxygen-rich fluorocarbon chemistry, the use of a polymerizing etchant is eliminated, making the manufacture of such devices simpler.
    Type: Application
    Filed: May 14, 1999
    Publication date: May 24, 2001
    Inventor: JAMES KENT NAYLOR