Patent number: 12277040
Abstract: In-place recovery of fatal system errors at virtualization hosts. A device identifies an occurrence of a fatal system error in the first instance of a host operating system (OS) executing in a computer system. The device determines to perform an in-place recovery for the fatal system error. The device performs the in-place recovery, including pausing the execution of a virtual machine (VM) by the first instance of the host OS, preserving a state of the VM within system memory of the computer system, and resuming the execution of the VM by a second instance of the host OS executing in the computer system based on the state of the VM that is preserved within the system memory of the computer system.
Type:
Grant
Filed:
June 7, 2023
Date of Patent:
April 15, 2025
Assignee:
Microsoft Technology Licensing, LLC
Inventors:
Binit Ranjan Mishra, Mukhtar Ahmed, Christina Marianne Curlette, Steven Adrian West, Gaurav Jagtiani, Naga Kiran Govindaraju, James George Cavalaris, Drew Douglas Cross, Jason Stewart Wohlgemuth, James Anthony Schwartz, Jr., Jennifer Marie Bourlier, Sri Harsha Kanukuntla, Emma Sutherland Boyd, Scott Chao-Chueh Lee, Vijaybalaji Madhanagopal, Terence Kwok Tak Chan, Yuri Dotsenko, Peter Hanpeng Jiang, Aacer Hatem Daken, Emily Nicole Wilson, Emily Cara Clemens, Cody Dean Hartwig, Raz Meir Aloni, Sharon Scarlet Tang, Minsang Kim, Shen Wang
Publication number: 20250098179
Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.
Type:
Application
Filed:
September 15, 2023
Publication date:
March 20, 2025
Inventors:
Abhishek A. Sharma, Van H. Le, Fatih Hamzaoglu, Juan G. Alzate-Vinasco, Nikhil Jasvant Mehta, Vinaykumar Hadagali, Yu-Wen Huang, Honore Djieutedjeu, Tahir Ghani, Timothy Jen, Shailesh Kumar Madisetti, Jisoo Kim, Wilfred Gomes, Kamal Baloch, Vamsi Evani, Christopher Wiegand, James Pellegren, Sagar Suthram, Christopher M. Pelto, Gwang Soo Kim, Babita Dhayal, Prashant Majhi, Anand Iyer, Anand S. Murthy, Pushkar Sharad Ranade, Pooya Tadayon, Nitin A. Deshpande