Patents by Inventor James L. Hafner

James L. Hafner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10318325
    Abstract: Embodiments relate to host-side cache migration. An aspect is a method that includes determining pre-fetch hints associated with a source cache that is local to a source host machine. The source cache includes pages of cache data for a virtual machine. The pre-fetch hints are sent to a pre-fetch planner to create a pre-fetch plan. The pre-fetch hints are sent based on migration of the virtual machine to a target host machine including a target cache that is local. At the source host machine, a cache migration request is received based on the pre-fetch plan. A first subset of the pages is sent from the source cache through a host-to-host communication channel to the target cache based on the cache migration request. A second subset of the pages is sent from the source cache through a host-storage communication channel to a shared storage to be relayed to the target cache.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Chambliss, Aayush Gupta, James L. Hafner, Maohua Lu, Nimrod Megiddo
  • Patent number: 10305516
    Abstract: Embodiments relate to a system with multiple erasure codes, and selecting and encoding for a write file with one of the codes to mitigate costs associated with storage recovery. The codes include a fast recovery code for frequently accessed data and a higher storage efficiency code for less frequently accessed data. State data is tracked to ascertain frequency of access to the file. One of the erasure codes is dynamically selected based on the tracked data, with the focus of the code select to lower recovery costs, and the data is encoded with the selected erasure code. Accordingly, the original coding of the write file is subject to change based on the tracked state data.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
  • Patent number: 10095595
    Abstract: In one embodiment, a system includes a cache storage device, a back-end storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive indication of failure of a primary cache server at a secondary cache server, the primary and secondary cache servers being configured to manage read requests and write requests for the back-end storage device. The logic is also configured to set the secondary cache server to a by-pass mode for read requests directed to any portions of the back-end storage device managed by the primary cache server prior to the failure. Moreover, the logic is configured to read an index of cache block descriptors (CBDs) managed by the primary cache server prior to the failure into a memory of the secondary cache server.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 10031803
    Abstract: A method for distributed coding in a storage array is presented. The method includes dividing data into multiple stripes for storage in a storage array including storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of a dimension t have even parity. Global parities are added to the hypercube such that a minimum distance of a code is enhanced.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Aayush Gupta, James L. Hafner, Steven R. Hetzler
  • Patent number: 10014881
    Abstract: Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
  • Publication number: 20180165195
    Abstract: In one embodiment, a computer-implemented method includes selecting a cache block descriptor (CBD) from amongst a plurality of CBDs stored to a cache storage device to defragment based on a determination of utilization of a particular fine block descriptor (FBD) having a first size that is allocated to the selected CBD. The cache storage device includes a free pool of FBDs having various sizes that is available for use in the plurality of CBDs. Also, the particular FBD having the first size has a lowest availability in the free pool of FBDs. Other methods, systems, and computer program products are described in accordance with additional embodiments.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 14, 2018
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9971692
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a plurality of access requests for data in the cache storage device, each request being directed to data in a common cache block descriptor (CBD). The CBD stores metadata corresponding to a storage location of the data in the cache storage device. The logic is also configured to update a request queue to reflect each access request from the plurality of access requests in an order in which individual access requests were received. Moreover, the logic is configured to delay at least some overlapping access requests.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9965390
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to select a cache block descriptor (CBD) from amongst a plurality of CBDs, the selected CBD including indications of being fragmented in the cache storage device. The logic is also configured to determine whether to defragment the selected CBD. Moreover, the logic is configured to defragment the selected CBD on the cache storage device in response to a decision to defragment the selected CBD.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Patent number: 9916249
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a write request including data to be written to the cache storage device. The logic is also configured to determine a size of the write request. Moreover, the logic is configured to select a chunk size from among a plurality of chunk sizes designated for storing data in the cache storage device. In addition, the logic is configured to allocate a fine block descriptor (FBD) having the selected chunk size to the write request.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20180052751
    Abstract: An apparatus comprises a storage controller coupled to at least one multi-region storage device. The at least one multi-region storage device comprises two or more storage regions, the two or more storage regions comprising a first storage region associated with a first set of failure characteristics and at least a second storage region associated with a second set of failure characteristics different than the first set of failure characteristics. The storage controller is configured to replicate in the second storage region at least a portion of data that is stored in the first storage region.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 22, 2018
    Inventors: BULENT ABALI, MOHAMMAD BANIKAZEMI, TIMOTHY J. CHAINER, JAMES L. HAFNER, DAN E. POFF, KRISHANKUMAR RAO SURUGUCCHI
  • Patent number: 9880913
    Abstract: An apparatus comprises a storage controller coupled to at least one multi-region storage device. The at least one multi-region storage device comprises two or more storage regions, the two or more storage regions comprising a first storage region associated with a first set of failure characteristics and at least a second storage region associated with a second set of failure characteristics different than the first set of failure characteristics. The storage controller is configured to replicate in the second storage region at least a portion of data that is stored in the first storage region.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, Mohammad Banikazemi, Timothy J. Chainer, James L. Hafner, Dan E. Poff, Krishnakumar Rao Surugucchi
  • Patent number: 9817757
    Abstract: In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170168897
    Abstract: A method for distributed coding in a storage array is presented. The method includes dividing data into multiple stripes for storage in a storage array including storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of a dimension t have even parity. Global parities are added to the hypercube such that a minimum distance of a code is enhanced.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Mario Blaum, Aayush Gupta, James L. Hafner, Steven R. Hetzler
  • Publication number: 20170168908
    Abstract: An apparatus comprises a storage controller coupled to at least one multi-region storage device. The at least one multi-region storage device comprises two or more storage regions, the two or more storage regions comprising a first storage region associated with a first set of failure characteristics and at least a second storage region associated with a second set of failure characteristics different than the first set of failure characteristics. The storage controller is configured to replicate in the second storage region at least a portion of data that is stored in the first storage region.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Bulent Abali, Mohammad Banikazemi, Timothy J. Chainer, James L. Hafner, Dan E. Poff, Krishnakumar Rao Surugucchi
  • Publication number: 20170139792
    Abstract: In one embodiment, a system includes a cache storage device, a back-end storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive indication of failure of a primary cache server at a secondary cache server, the primary and secondary cache servers being configured to manage read requests and write requests for the back-end storage device. The logic is also configured to set the secondary cache server to a by-pass mode for read requests directed to any portions of the back-end storage device managed by the primary cache server prior to the failure. Moreover, the logic is configured to read an index of cache block descriptors (CBDs) managed by the primary cache server prior to the failure into a memory of the secondary cache server.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170139829
    Abstract: In one embodiment, a system includes a back-end storage device, a cache storage device, and a processor and logic integrated with and/or executable by the processor. The logic is configured to store data to the cache storage device using fine block descriptors (FBDs) configured for fine-grained mapping of variable-size cache allocations. The logic is also configured to store data to the back-end storage device using cache block descriptors (CBDs) configured for coarse-grained mapping of large blocks of data. At least some FBDs are smaller in size than any of the CBDs, and all FBDs are equal to or smaller in size than any of the CBDs.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170139834
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a write request including data to be written to the cache storage device. The logic is also configured to determine a size of the write request. Moreover, the logic is configured to select a chunk size from among a plurality of chunk sizes designated for storing data in the cache storage device. In addition, the logic is configured to allocate a fine block descriptor (FBD) having the selected chunk size to the write request.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170139830
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to select a cache block descriptor (CBD) from amongst a plurality of CBDs, the selected CBD including indications of being fragmented in the cache storage device. The logic is also configured to determine whether to defragment the selected CBD. Moreover, the logic is configured to defragment the selected CBD on the cache storage device in response to a decision to defragment the selected CBD.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170139832
    Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a plurality of access requests for data in the cache storage device, each request being directed to data in a common cache block descriptor (CBD). The CBD stores metadata corresponding to a storage location of the data in the cache storage device. The logic is also configured to update a request queue to reflect each access request from the plurality of access requests in an order in which individual access requests were received. Moreover, the logic is configured to delay at least some overlapping access requests.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 18, 2017
    Inventors: Aayush Gupta, James L. Hafner, Mohit Saxena
  • Publication number: 20170077961
    Abstract: Embodiments relate to dynamically selecting an erasure code. State data is tracked to ascertain frequency of file access. One of at least two erasure codes are selected based on the tracked state data in order to lower data recovery cost. The erasure code may be selected as either a product code or a local reconstruction code. Each erasure code includes a mode that is either a fast code or a compact code. The fast code features a low recovery cost and the compact code features a low storage overhead for less frequently accessed data. Data is encoded with one of the selected erasure codes and one of the modes of the selected erasure code. Data blocks are dynamically converted between the fast and compact codes of the selected erasure code responsive to a workload change.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Applicant: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia