Patents by Inventor James L. Hafner
James L. Hafner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8583866Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node.Type: GrantFiled: February 22, 2010Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: David D. Chambliss, James L. Hafner, Tarun Thakur
-
Patent number: 8583868Abstract: Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller.Type: GrantFiled: August 29, 2011Date of Patent: November 12, 2013Assignee: International Business MachinesInventors: Wendy A. Belluomini, Binny S. Gill, James L. Hafner, Steven R. Hetzler, Venu G. Nayar, Daniel F. Smith, Krishnakumar Rao Surugucchi
-
Patent number: 8578094Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node.Type: GrantFiled: August 14, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: David D. Chambliss, James L. Hafner, Tarun Thakur
-
Publication number: 20130205168Abstract: Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe.Type: ApplicationFiled: July 18, 2012Publication date: August 8, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
-
Publication number: 20130205181Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
-
Patent number: 8433979Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr?1 erasures in any one of the remaining r?1 rows, up to tr?2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.Type: GrantFiled: February 28, 2011Date of Patent: April 30, 2013Assignee: International Business Machines CorporationInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
-
Publication number: 20130054873Abstract: Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wendy A. Belluomini, Binny S. Gill, James L. Hafner, Steven R. Hetzler, Venu G. Nayar, Daniel F. Smith, Krishnakumar Rao Surugucchi
-
Publication number: 20130024625Abstract: Provided are a computer program product, sequential access storage device, and method for managing data in a sequential access storage device receiving read requests and write requests from a system with respect to tracks stored in a sequential access storage medium. A prefetch request indicates prefetch tracks in the sequential access storage medium to read from the sequential access storage medium. The accessed prefetch tracks are cached in a non-volatile storage device integrated with the sequential access storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A read request is received for the prefetch tracks following the caching of the prefetch tracks, wherein the prefetch request is designated to be processed at a lower priority than the read request with respect to the sequential access storage medium. The prefetch tracks are returned from the non-volatile storage device to the read request.Type: ApplicationFiled: May 24, 2012Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, James L. Hafner
-
Publication number: 20130024613Abstract: Provided are a computer program product, system, and method for prefetching data tracks and parity data to use for destaging updated tracks. A write request is received including at least one updated track to the group of tracks. The at least one updated track is stored in a first cache device. A prefetch request is sent to the at least one sequential access storage device to prefetch tracks in the group of tracks to a second cache device. A read request is generated to read the prefetch tracks following the sending of the prefetch request. The read prefetch tracks returned to the read request from the second cache device are stored in the first cache device. New parity data is calculated from the at least one updated track and the read prefetch tracks.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, James L. Hafner
-
Publication number: 20130024627Abstract: Provided are a computer program product, system, and method for prefetching data tracks and parity data to use for destaging updated tracks. A write request is received including at least one updated track to the group of tracks. The at least one updated track is stored in a first cache device. A prefetch request is sent to the at least one sequential access storage device to prefetch tracks in the group of tracks to a second cache device. A read request is generated to read the prefetch tracks following the sending of the prefetch request. The read prefetch tracks returned to the read request from the second cache device are stored in the first cache device. New parity data is calculated from the at least one updated track and the read prefetch tracks.Type: ApplicationFiled: April 27, 2012Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, James L. Hafner
-
Publication number: 20130024624Abstract: Provided are a computer program product, sequential access storage device, and method for managing data in a sequential access storage device receiving read requests and write requests from a system with respect to tracks stored in a sequential access storage medium. A prefetch request indicates prefetch tracks in the sequential access storage medium to read from the sequential access storage medium. The accessed prefetch tracks are cached in a non-volatile storage device integrated with the sequential access storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A read request is received for the prefetch tracks following the caching of the prefetch tracks, wherein the prefetch request is designated to be processed at a lower priority than the read request with respect to the sequential access storage medium. The prefetch tracks are returned from the non-volatile storage device to the read request.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, James L. Hafner
-
Publication number: 20120331367Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r-1 rows, up to tr-2 erasures in any one of the remaining r-2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.Type: ApplicationFiled: July 31, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
-
Publication number: 20120311255Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Information is stored as a stripe including a collection of a data strips and associated parity strips, the stripe distributed across data and parity nodes. Each data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the collection of data strips. A driver node initiates a full-stripe-write parity update protocol for maintaining parity coherency in conjunction with other nodes, to keep the relevant parity strips coherent. Parity is determined directly by computing parity strips for all data strips of a stripe. Any node may function as a driver node.Type: ApplicationFiled: August 14, 2012Publication date: December 6, 2012Applicant: International Business Machines CorporationInventors: David D. CHAMBLISS, James L. Hafner, Tarun Thakur
-
Publication number: 20120297127Abstract: Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.Type: ApplicationFiled: July 19, 2012Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wendy A. Belluomini, Binny S. Gill, James L. Hafner, Steven R. Hetzler, Assaf Nitzan, Eyal Lotem, Venu G. Nayar, Edi Shmueli, Daniel F. Smith
-
Publication number: 20120297113Abstract: Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.Type: ApplicationFiled: May 20, 2011Publication date: November 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wendy A. Belluomini, Binny S. Gill, James L. Hafner, Steven R. Hetzler, Assaf Nitzan, Eyal Lotem, Venu G. Nayar, Edi Shmueli, Daniel F. Smith
-
Publication number: 20120221920Abstract: Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler, Daniel F. Smith
-
Publication number: 20120221926Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r?1 rows, up to tr-2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
-
Patent number: 8156368Abstract: Rebuilding lost data in a distributed redundancy data storage system including multiple nodes, is provided. User data is stored as a collection of stripes, each stripe comprising a collection of data strips and associated parity strips, the stripes distributed across multiple corresponding data owner nodes and multiple corresponding parity owner nodes. A data owner node maintains the associated data strip holding a first copy of data, and a parity owner node maintains a parity strip holding a parity for the collection of data strips. Upon detecting a failure condition, the owner node initiates a rebuilding protocol for recovery of lost data and/or parity it owns. The protocol includes reconstruction of lost data or parity by a computation involving data and/or parity from a recovery strip set in a stripe, wherein a recovery strip set contains at least one surviving data or parity strip. The recovery strip set for a lost data strip contains at least one surviving parity strip.Type: GrantFiled: February 22, 2010Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: David D. Chambliss, James L. Hafner, Tarun Thakur
-
Patent number: 8103904Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes. Each node comprises a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe including a collection of at least a data strip and associated parity strips, the stripes distributed across a primary data node and multiple corresponding parity nodes. A read-other parity update protocol maintains parity coherency. The primary data node for each data strip drives parity coherency with the corresponding parity nodes, independently of other data nodes, in keeping relevant parity strips for the primary data node coherent. A parity value is determined based on data other than a difference between new data and existing data. A new parity value is based on new data and dependent data, wherein with respect to one data value, dependent data comprises other data encoded in a corresponding parity value.Type: GrantFiled: February 22, 2010Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: James L. Hafner, Tarun Thakur
-
Patent number: 8103903Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes, each node comprising a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe including a collection of multiple data strips and associated parity strips, the stripes distributed across multiple corresponding primary data nodes and multiple corresponding parity nodes. A primary data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the multiple data strips. A read-modify-write parity update protocol is performed for maintaining parity coherency, the primary data node driving parity coherency with its corresponding parity nodes, independently of other data nodes, in order to keep its relevant parity strips coherent.Type: GrantFiled: February 22, 2010Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: James L. Hafner, Prashant Pandey, Tarun Thakur