Abstract: Aspects provide for reducing the size and cost of a compound semiconductor power FET device while increasing yield and maintaining current handling capabilities of the FET by distributing portions of the current in parallel to sections the source and drain fingers to maintain a low current density, and applying the gate signal to both ends of the gate fingers to increase yield. The current to be handled by the FET may be divided among a set of electrodes arrayed along the width of the source or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. The current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.

Abstract: Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.

Abstract: A semiconductor device having at least one lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect having a sloped wall that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel. In a related but alternative embodiment, the first contact is a source contact and the second contact is a drain contact for the semiconductor device.

Abstract: A n-bit digitally controlled phase shifter for controlling the phase of an applied signal over the range of 0.degree. to 360.degree. includes n, cascade interconnected phase shifter stages. Each phase shifter stage is formed on a semi-insulating substrate having a pair of field effect transistors and a pair of transmission lines formed thereon. Each field effect transistor (FET), includes a pair of gate electrodes, a drain electrode, and a source electrode, connected in a common (grounded) source configuration. Each transmission line is coupled between a corresponding one of the drain electrodes and a common output port. The lengths of the transmission lines are selected to provide two paths having an electrical pathlength corresponding to a phase shift of .phi..sub.1 or a phase shift of .phi..sub.1 +.DELTA..phi..sub.1 where .DELTA..phi..sub.i is the phase shift increment of the i.sup.th stage. A first one of the gate electrodes of each field effect transistor is fed by the applied signal.

Abstract: Lumped passive components including a capacitor having a silicon nitride dielectric, a tantalum film resistor, and a capacitor having a tantalum oxide dielectric are formed on a semi-insulating substrate by first providing an insulating layer, here of silicon nitride, over the substrate and metal contacts having previously been formed on such substrate. The metal contacts provide a first plate for each one of such capacitors. A tantalum layer is reactively sputtered on the insulating layer, and a protective masking layer is next provided on such tantalum layer. An area where the anodized tantalum capacitor is to be formed is then opened in the protective masking layer over a selected one of the metal contacts. A portion of the tantalum is anodized in such area to form an area of a tantalum oxide (Ta.sub.2 O.sub.5). The area where the tantalum oxide is formed is confined generally to the area in the tantalum layer over the contact.

Abstract: A phase shifter includes three cascade interconnected phase shift stages. Each stage includes a quadrature coupler and a pair of field effect transistors (FET), having a pair of gates, a drain, and a source, connected in a common (grounded) source configuration. The drain of each FET is coupled to an input port of the quadrature coupler to provide two signal paths having an electrical pathlength difference corresponding to a 90.degree. differential phase shift. In the third stage, a length of transmission line is coupled between a drain of one of the FET's and one input port of the coupler to provide a signal path having an electrical pathlength corresponding to a 180.degree. phase shift. An input signal is fed to one of the gates of each FET of the first stage, and voltage level control signals are fed to the second one of gates of each FET of the first stage, to control the amplitude of the signal coupled to each drain.

Abstract: A field effect transistor is provided wherein a semiconductor body has a central source region and a plurality of drain regions disposed about the periphery of the central source region. A gate region, common to at least a portion of the plurality of drain regions, is also formed in the body. With such arrangement an efficient multi-drain field effect transistor is provided through the use of a central source electrode formed on the semiconductor body.