Abstract: A magnetic transistor circuit representing the data ‘1’ and ‘0’ of the binary system comprises a routing line and a magnetic transistor unit. The routing line has a current going through with a first current direction or a second current direction, wherein the first current direction and the second current direction are opposite to represent the data ‘1’ and the data ‘0’ respectively. The magnetic transistor unit couples to the routing line at an output end to control the direction of the current going through the routing line.

Abstract: A magnetic OR/NAND circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘OR’ and ‘NAND’ logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a third magnetic section and a fourth magnetic section, wherein the third magnetic section couples to a low voltage end, and the fourth magnetic section couples to the second magnetic section of the first magnetic transistor. The third magnetic transistor has a fifth magnetic section and a sixth magnetic section, wherein the fifth magnetic section couples with the second magnetic section and the fourth magnetic section together, and the sixth magnetic section couples to an input/output end.

Abstract: A magnetic AND/NOR circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘AND’ and ‘NOR’ logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: The method for reducing word line currents in magnetoresistive random access memory (MRAM) includes disposing the MRAM bit between a pair of word lines according to a magnetic field strength is increased when a distance between a magnetic section and its corresponding word line is decreased.

Abstract: A magnetic random access memory (MRAM) device includes sense lines, a selector, a reading circuit and a writing circuit. Each sense line is coupled to one or more MRAM cells. The selector is used to select one of the sense lines to allow a read or write operation. The reading circuit is coupled to the sense lines and provides a first sense current to the selected sense line during the read operation. The writing circuit is coupled to the sense lines and provides a second sense current to the selected sense line during the write operation.

Abstract: A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlying power plane metal.

Abstract: A variable timing system for a magnetoresistive random access memory circuit (MRAM IC) is embedded in an MRAM IC and includes a number of timing control circuits, where each timing control circuit generates a timing control signal. A number of variable timing circuits are each coupled to receive at least two of the timing control signals, and each of the number of timing circuits outputs a variable timing in response to the timing control signals. At least one MRAM timing driver is connected to receive the variable timing.

Abstract: A method and apparatus for discharging and equalizing sense lines embedded in a magnetoresistive random access memory integrated circuit (MRAM IC) includes using a current source connected to a current source node. A sense line is connected to the current source node. A bit decode element is coupled to turn on and allow the current source to source a current through the sense line so as to set the current source node to a selected voltage. A discharger is connected at a first terminal to the current source node so as to accelerate discharge of the current source node when the current source turns off.

Abstract: A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

Abstract: Metal plugs located in a planar dielectric layer, under a GMR stack layer, are used to connect the nonmagnetic conducting layer of the GMR stack layer and a conducting layer under the planar dielectric layer.

Abstract: A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word line driver employ pull up and pull down transistors that configured to drive current on the selected word line in either a read or write ‘0’ direction or a read or write ‘1’ direction in response to control signals that allow reliable magnetic memory operation. An address decoder selects and activates a multiplexer in the sub word line driver to coordinate the current drive. The main word line driver employs current mirrors, transistor switches, and logic control to prevent direct Vdd to Vss shorting in transitioning from ‘0’ and ‘1’, and read and write data storage operations.

Abstract: A word current source for a magnetoresistive random access memory (MRAM) circuit includes an n-channel transistor including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the MRAM circuit. A positive supply voltage is coupled to the MRAM circuit so as to allow current to flow through the MRAM circuit when an activation signal is applied to the gate by a control circuit.

Abstract: A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and the conductive layers. Thus, a conventional deep tungsten plug process, interconnecting two conductive layers, is eliminated.

Abstract: A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection. The extended address transition detection circuit has an extended transition detection signal output. The magnetic random access memory has a timing controller with a timing control input connected to the address transition detection signal output. The chip enable input, the chip write enable input, the data bus connection, and the address bus connection are buffered and driven off chip.

Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.

Abstract: A memory comprises a plurality of memory units electrically connected. Each of the memory units comprises a pull-down transistor, a plurality of column lines and a selector. Each of the column lines has at least one bit. The selector is electrically connected between the pull-down transistor and the column lines. The selector is arranged to select one from the column lines to be accessed by the pull-down transistor. This results in a memory design that is faster, has more capability, is cheaper to build, quieter, and lower power.

Abstract: An emergency lighting device adapted to be quickly and easily mounted and installed. In one embodiment, a mounting member of the device is first mounted to a desired structure and connected to an external power supply. Once mounted and completed, and emergency lighting assembly is secured to the mounting member. In certain embodiments, securing the emergency lighting assembly to the mounting member connects the device to the external power supply and energizes the device.

Abstract: A method of flow control management of data packets in a switch. The method has the steps of determining each time data is being written to memory in order to calculate a memory used amount; determining each time data is being freed from memory in order to calculate a memory freed amount; and calculating how much total memory is being used using the memory freed amount and the memory used amount. A comparison is made comparing the total memory being used to a first predetermined threshold. When the first predetermined threshold is reached a first threshold command is issued indicating that the first predetermined threshold has been reached.

Abstract: A system and method for self-adaptive redundancy choice logic uses BIST data to determine if a memory is functional. If a portion of the memory is not functional, the system and method selects a redundant memory section for use. A BIST is then run a second time to confirm the functionality of the selected redundant memory section.