Abstract: A system for dispensing a detergent solution from a solid detergent into a dishwasher includes a dispenser that can collect water sprayed into the dishwasher and use the collected water to produce the detergent solution by dissolving a portion of the solid detergent, controlling the amount of the detergent solution produced, and releasing the produced detergent solution between cleaning cycles. The dispenser can perform these functions automatically without being electrically powered.

Abstract: A composition can photocatalytically reduce carbon dioxide.

Abstract: A system for dispensing a detergent solution from a solid detergent into a dishwasher includes a dispenser that can collect water sprayed into the dishwasher and use the collected water to produce the detergent solution by dissolving a portion of the solid detergent, controlling the amount of the detergent solution produced, and releasing the produced detergent solution between cleaning cycles. The dispenser can perform these functions automatically without being electrically powered.

Abstract: A composition can photocatalytically reduce carbon dioxide.

Abstract: A composition can photocatalytically reduce carbon dioxide.

Abstract: A system for dispensing a detergent solution from a solid detergent into a dishwasher includes a dispenser that can collect water sprayed into the dishwasher and use the collected water to produce the detergent solution by dissolving a portion of the solid detergent, controlling the amount of the detergent solution produced, and releasing the produced detergent solution between cleaning cycles. The dispenser can perform these functions automatically without being electrically powered.

Abstract: A composition can photocatalytically reduce carbon dioxide.

Abstract: The Adaptable Pulse Position Modulation (APPM) optical communication system and process facilitate wireless communications through turbid mediums including, but not limited to, smoke, airborne dust, mist, fog, clouds, water, seawater and water-to-air (air-to-water) interfaces by controlling the signal gain at the optical detector and controlling of the signal encoding to allow high data rate operation when the signal to noise ratio is high. The system also supports signal encoding redundancy to maintain good connectivity at the cost of the communication channel data rate as the signal to noise degrades.

Abstract: The Adaptable Pulse Position Modulation (APPM) optical communication system and process facilitate wireless communications through turbid mediums including, but not limited to, smoke, airborne dust, mist, fog, clouds, water, seawater and water-to-air (air-to-water) interfaces by controlling the signal gain at the optical detector and controlling of the signal encoding to allow high data rate operation when the signal to noise ratio is high. The system also supports signal encoding redundancy to maintain good connectivity at the cost of the communication channel data rate as the signal to noise degrades.

Abstract: A system useful in providing communications with automatic data collection (ADC) devices employs an antenna located in a potentially hazardous environment, a radio circuit located in a non-hazardous environment, and a coupling apparatus to provide an interface between the antenna and the radio circuit that prevents electrical discharges from occurring in the potentially hazardous environment.

Abstract: The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.

Abstract: A system useful in providing communications with automatic data collection (ADC) devices employs an antenna located in a potentially hazardous environment, a radio circuit located in a non-hazardous environment, and a coupling apparatus to provide an interface between the antenna and the radio circuit that prevents electrical discharges from occurring in the potentially hazardous environment.

Abstract: An adjustable oscillator for dynamically optimizing a damping coefficient of a PLL circuit including a gain controlled oscillator circuit and a damping controller. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals and generates a third clock signal which has a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator circuit has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator circuit. The damping controller adjusts gain of the oscillator circuit in response to changes of the clock multiplier to minimize variation of the damping coefficient.

Abstract: A damping coefficient correction mechanism for a PLL circuit including a gain controlled oscillator circuit, a damping controller, and gain compensation logic. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals for generating a third clock signal having a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator. The damping controller adjusts gain of the oscillator in response to changes of the clock multiplier. The gain compensation logic is programmable and adjusts the gain control signal.

Abstract: A damping coefficient variation mechanism for a PLL including a bias controller, a gain control circuit, and an oscillator circuit. The PLL receives an input clock signal and provides an output clock at a frequency that is the frequency of the input clock multiplied by a clock multiplier. The bias controller has an input receiving a loop control signal and an output providing one or more bias signals. The gain control circuit has bias inputs receiving the bias signals, a gain control input receiving a gain control value, and an output providing a control signal. The oscillator circuit has an input receiving the control signal and an output providing the output clock signal. The gain control circuit provides the control signal to adjust frequency of the output clock signal based on the loop control signal at a gain determined by the gain control value.

Abstract: A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.

Abstract: A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.

Abstract: An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node high when the approximately symmetric clock signal is low, and discharges the pre-charged node to a low state if the logic function evaluates when the approximately symmetric clock signal is high, and keeps the pre-charged node high if the logic function fails to evaluate when the approximately symmetric clock signal is high, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is high.

Abstract: An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node.

Abstract: A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.