Abstract: An overvoltage protection circuit for a receiver including first and second pass devices and a protection control circuit. The receiver detects the state of a high voltage level input signal using a switching threshold based on a low voltage level source voltage. The receiver has a maximum voltage limit between the low and high voltage levels. The first pass device passes the input signal up to a first voltage level below the source voltage. The second pass device is effectively coupled in parallel with the first pass device. The protection control circuit controls the second pass device to allow the input signal to rise above the first voltage level up to a threshold voltage that is above the source voltage sufficient to meet the logic switching threshold yet below the maximum voltage limit.

Abstract: A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation devices at a pre-charged node and evaluates a logic function based on at least one input data signal. The latching logic asserts the logic state of an output node based on the state of the pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of an evaluation complete signal, which is a delayed and inverted version of the clock signal. The output node is returned to zero between evaluation periods. A footless latching domino circuit may be added to convert the RTZ output to a registered output signal.

Abstract: A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged node and an evaluation node. The delayed inversion logic outputs a complete signal that is a delayed and inverted version of the clock signal. The dynamic evaluator, coupled between the pre-charged and evaluation nodes, evaluates a logic function based on a data signal during an evaluation period between operative edges of the clock and complete signals. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps the pre-charged node to prevent perturbations of the data signal from propagating to the output node.